Data Sheet

PYNQ-Z1 Board Reference Manual
Copyright Digilent, Inc. All rights reserved.
Other product and company names mentioned may be trademarks of their respective owners.
Page 17 of 25
A PDM signal is generated from an analog signal through a process called delta-sigma modulation. A simple
idealized circuit of delta-sigma modulator is shown in Figure 13.1.2.
Figure 13.1.2. PDM Delta-Sigma Modulator.
Sum
Integrator Out
Flip-flop Output
0.4-0=0.4
0+0.4=0.4
0
0.4-0=0.4
0.4+0.4=0.8
1
0.4-1=-0.6
0.8-0.6=0.2
0
0.4-0=0.4
0.2+0.4=0.6
1
0.4-1=-0.6
0.6-0.6=0
0
0.4-0=0.4
0+0.4=0.4
0
0.4-0=0.4
0.4+0.4=0.8
1
0.4-1=-0.6
0.8-0.6=0.2
0
Table 13.1.1. Sigma Delta Modulator with a 0.4Vdd input.
To keep things simple, assume that the analog input and digital output have the same voltage range 0~Vdd. The
input of the flip-flop acts like a comparator (any signal above Vdd/2 is considered as ‘1’ and any input bellow Vdd/2
is considered ‘0’). The input of the integral circuit is the difference of the input analog signal and the PDM signal of
the previous clock cycle. The integral circuit then integrates both of these inputs, and the output of the integral
circuit is sampled by a D-Flip-flop. Table 13.1.1 shows the function of the delta-sigma modulator with an input of
0.4Vdd.
Note that the average of the flip-flop output equals the value of the input analog signal. So in order to get the
value of analog input, all that is needed is a counter that counts the ‘1’s for a certain period of time.
13.2 Microphone Digital Interface Timing
The clock input of the microphone can range from 1 MHz to 3.3 MHz based on the sampling rate and data
precision requirement of the applications. The L/R Select signal must be set to a valid level, depending on which
edge of the clock the data bit will be read. A low level on L/RSEL makes data available on the rising edge of the
clock, while a high level corresponds to the falling edge of the clock, as shown in Fig. 13.2.1. Note that on the
PYNQ-Z1, the L/RSEL signal is permanently tied low, so data is always made available on the rising edge (as seen
with the DATA 1 signal in Fig. 13.2.1).
Figure 13.2.1. Microphone Signal Timing.