Data Sheet

PYNQ-Z1 Board Reference Manual
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Page 18 of 25
The typical value of the clock frequency is 2.4 MHz. Assuming that the application requires 7-bit precision and 24
KHz, there can be two counters that count 128 samples at 12 KHz, as shown in Fig. 13.2.2.
Figure 13.2.2. Example PDM Circuit.
14 Mono Audio Output
The on-board audio jack (J13) is driven by a Sallen-Key Butterworth Low-pass 4th Order Filter that provides mono
audio output. The circuit of the low-pass filter is shown in Fig. 14.1. The input of the filter (AUD_PWM) is
connected to the Zynq PL pin R18. A digital input will typically be a pulse-width modulated (PWM) or pulse density
modulated (PDM) open-drain signal produced by the FPGA. The signal needs to be driven low for logic ‘0’ and left
in high-impedance for logic ‘1’. An on-board pull-up resistor to a clean analog 3.3V rail will establish the proper
voltage for logic ‘1’. The low-pass filter on the input will act as a reconstruction filter to convert the pulse-width
modulated digital signal into an analog voltage on the audio jack output.
Figure 14.1. Audio Output Circuit.
The Audio shut-down signal (AUD_SD) is used to mute the audio output. It is connected to Zynq PL pin T17. To use
the audio output, this signal must be driven to logic high.
The frequency response of SK Butterworth Low-Pass Filter is shown in Fig. 14.2. The AC analysis of the circuit is
done using NI Multisim 12.0.