Data Sheet

PYNQ-Z1 Board Reference Manual
Copyright Digilent, Inc. All rights reserved.
Other product and company names mentioned may be trademarks of their respective owners.
Page 20 of 25
Figure 14.1.2. PWM Output Voltage.
15 Reset Sources
15.1 Power-on Reset
The Zynq PS supports external power-on reset signals. The power-on reset is the master reset of the entire chip.
This signal resets every register in the device capable of being reset. The PYNQ-Z1 drives this signal from the
PGOOD signal of the TPS65400 power regulator in order to hold the system in reset until all power supplies are
valid.
15.2 Program Push Button Switch
A PROG push switch, labeled PROG, toggles Zynq PROG_B. This resets the PL and causes DONE to be de-asserted.
The PL will remain unconfigured until it is reprogrammed by the processor or via JTAG.
15.3 Processor Subsystem Reset
The external system reset, labeled SRST, resets the Zynq device without disturbing the debug environment. For
example, the previous break points set by the user remain valid after system reset. Due to security concerns,
system reset erases all memory content within the PS, including the OCM. The PL is also cleared during a system
reset. System reset does not cause the boot mode strapping pins to be re-sampled.
The SRST button also causes the CK_RST signal to toggle in order to trigger a reset on any attached shields.
16 Pmod Ports
Pmod ports are 2×6, right-angle, 100-mil spaced female connectors that mate with standard 2×6 pin headers. Each
12-pin Pmod port provides two 3.3V VCCsignals (pins 6 and 12), two Ground signals (pins 5 and 11), and eight logic
signals, as shown in Figure 16.1. The VCC and Ground pins can deliver up to 1A of current, but care must be taken
not to exceed any of the power budgets of the onboard regulators or the external power supply (see the 3.3V rail
current limits listed in the “Power Supplies” section).
Figure 16.1. Pmod Port Diagram.