Data Sheet

PYNQ-Z1 Board Reference Manual
Copyright Digilent, Inc. All rights reserved.
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Page 23 of 25
Pin Name
Shield Function
PYNQ-Z1 Connection
XVREF
XADC Analog
Voltage Reference
Connected to 1.25 V, 25mA rail used to drive the XADC
voltage reference on the Zynq (VREFP)
N/C
Not Connected
Not Connected
IOREF
Digital I/O Voltage
reference
Connected to the PYNQ-Z1 3.3V Power Rail (See the “Power
Supplies” section)
RST
Reset to Shield
Connected to the red “SRST” button and MIO pin 12 of the
Zynq. When JP1 is shorted, it is also connected to the DTR
signal of the FTDI USB-UART bridge.
3V3
3.3V Power Rail
Connected to the PYNQ-Z1 3.3V Power Rail (See the “Power
Supplies” section)
5V0
5.0V Power Rail
Connected to the PYNQ-Z1 5.0V Power Rail (See the “Power
Supplies” section)
GND, G
Ground
Connected to the Ground plane of PYNQ-Z1
VIN
Power Input
Connected in parallel with the external power supply
connector (J18).
Table 17.1. Shield Pin Descriptions.
17.1 Shield Digital I/O
The pins connected directly to the Zynq PL can be used as general purpose inputs or outputs. These pins include
the I2C, SPI, and general purpose I/O pins. There are 200 Ohm series resistors between the FPGA and the digital
I/O pins to help provide protection against accidental short circuits (with the exception of the AN5-AN0 signals,
which have no series resistors, and the AN6-AN12 signals, which have 100 Ohm series resistors). The absolute
maximum and recommended operating voltages for these pins are outlined in the table below.
Absolute
Minimum
Voltage
Recommended Minimum
Operating Voltage
Recommended Maximum
Operating Voltage
Absolute
Maximum
Voltage
Powered
-0.4 V
-0.2 V
3.4 V
3.75 V
Unpowered
-0.4 V
N/A
N/A
0.55 V
Table 17.1.1. Shield Digital Voltages.
For more information on the electrical characteristics of the pins connected to the Zynq PL, please see the Zynq-
7000 datasheet from Xilinx.