Datasheet

NetFPGA-1G-CML™ Board Reference Manual
Copyright Digilent, Inc. All rights reserved.
Other product and company names mentioned may be trademarks of their respective owners.
Page 17 of 21
NET rgmii_rxd_1[3]
LOC = D13
IOSTANDARD = LVCMOS18;
NET rgmii_txd_1[0]
LOC = G12
IOSTANDARD = LVCMOS18;
NET rgmii_txd_1[1]
LOC = F13
IOSTANDARD = LVCMOS18;
NET rgmii_txd_1[2]
LOC = F12
IOSTANDARD = LVCMOS18;
NET rgmii_txd_1[3]
LOC = H11
IOSTANDARD = LVCMOS18;
NET rgmii_rx_ctl_1
LOC = C13
IOSTANDARD = LVCMOS18;
NET rgmii_rxc_1
LOC = E11
IOSTANDARD = LVCMOS18;
NET rgmii_tx_ctl_1
LOC = F10
IOSTANDARD = LVCMOS18;
NET rgmii_txc_1
LOC = E13
IOSTANDARD = LVCMOS18;
NET rgmii_rxd_2[0]
LOC = B15
IOSTANDARD = LVCMOS18;
NET rgmii_rxd_2[1]
LOC = F14
IOSTANDARD = LVCMOS18;
NET rgmii_rxd_2[2]
LOC = C14
IOSTANDARD = LVCMOS18;
NET rgmii_rxd_2[3]
LOC = H12
IOSTANDARD = LVCMOS18;
NET rgmii_txd_2[0]
LOC = J13
IOSTANDARD = LVCMOS18;
NET rgmii_txd_2[1]
LOC = G14
IOSTANDARD = LVCMOS18;
NET rgmii_txd_2[2]
LOC = H14
IOSTANDARD = LVCMOS18;
NET rgmii_txd_2[3]
LOC = H13
IOSTANDARD = LVCMOS18;
NET rgmii_rx_ctl_2
LOC = A15
IOSTANDARD = LVCMOS18;
NET rgmii_rxc_2
LOC = G11
IOSTANDARD = LVCMOS18;
NET rgmii_tx_ctl_2
LOC = J11
IOSTANDARD = LVCMOS18;
NET rgmii_txc_2
LOC = D14
IOSTANDARD = LVCMOS18;
NET rgmii_rxd_3[0]
LOC = A13
IOSTANDARD = LVCMOS18;
NET rgmii_rxd_3[1]
LOC = C9
IOSTANDARD = LVCMOS18;
NET rgmii_rxd_3[2]
LOC = D11
IOSTANDARD = LVCMOS18;
NET rgmii_rxd_3[3]
LOC = C11
IOSTANDARD = LVCMOS18;
NET rgmii_txd_3[0]
LOC = D10
IOSTANDARD = LVCMOS18;
NET rgmii_txd_3[1]
LOC = G10
IOSTANDARD = LVCMOS18;
NET rgmii_txd_3[2]
LOC = D9
IOSTANDARD = LVCMOS18;
NET rgmii_txd_3[3]
LOC = F9
IOSTANDARD = LVCMOS18;
NET rgmii_rx_ctl_3
LOC = A12
IOSTANDARD = LVCMOS18;
NET rgmii_rxc_3
LOC = C12
IOSTANDARD = LVCMOS18;
NET rgmii_tx_ctl_3
LOC = F8
IOSTANDARD = LVCMOS18;
NET rgmii_txc_3
LOC = J10
IOSTANDARD = LVCMOS18;
NET rgmii_rxd_4[0]
LOC = B11
IOSTANDARD = LVCMOS18;
NET rgmii_rxd_4[1]
LOC = A10
IOSTANDARD = LVCMOS18;
NET rgmii_rxd_4[2]
LOC = B10
IOSTANDARD = LVCMOS18;
NET rgmii_rxd_4[3]
LOC = A9
IOSTANDARD = LVCMOS18;
NET rgmii_txd_4[0]
LOC = A8
IOSTANDARD = LVCMOS18;
NET rgmii_txd_4[1]
LOC = D8
IOSTANDARD = LVCMOS18;
NET rgmii_txd_4[2]
LOC = G9
IOSTANDARD = LVCMOS18;
NET rgmii_txd_4[3]
LOC = H9
IOSTANDARD = LVCMOS18;
NET rgmii_rx_ctl_4
LOC = B12
IOSTANDARD = LVCMOS18;
NET rgmii_rxc_4
LOC = E10
IOSTANDARD = LVCMOS18;
NET rgmii_tx_ctl_4
LOC = H8
IOSTANDARD = LVCMOS18;
NET rgmii_txc_4
LOC = B9
IOSTANDARD = LVCMOS18;
PIC Interface
Port Name
IO Location
IO Standard Type
NET pic2fpga_sck
LOC = AA17
IOSTANDARD = LVCMOS18;
NET pic2fpga_sdo
LOC = V16
IOSTANDARD = LVCMOS18;
NET pic2fpga_ss_n
LOC = W16
IOSTANDARD = LVCMOS18;