Manual

ManualsBrandsDigilent ManualsSingle board computersNETFPGA-SUME FPGA Board

1300 Henley Court

Pullman, WA 99163

509.334.6306

www.digilentinc.com

NetFPGA-SUME™ Reference Manual

Revised April 6, 2015

This manual applies to the NetFPGA-SUME rev. C

DOC#: 502-301

Other product and company names mentioned may be trademarks of their respective owners.

Page 1 of 18

Overview

FPGA, the NetFPGA-SUME is an ideal

platform for high-performance and

high-density networking design.

32 GTH serial transceivers have been

used to provide access to 8 lanes of

end-point PCI-E (Gen3 x8), 4 SFP+

(10Gbps) ports, 2 SATA-III ports

(6Gbps), and 18 data-rate-adjustable

GTH ports through a HPC-FMC

connector and a QTH connector.

Wide high-speed memory interfaces in the form of three 72 MBit QDRII+ SRAMs with 36 bit buses and two 4GB

DDR3 SODIMMs with 64 bit buses provide an ideal memory solution for common networking applications.

FPGA

 Xilinx Virtex-7 XC7V690T FFG1761-3

Memory

 Two 4GB DDR3 SODIMMs (MT8KTF51264Hz-

1G9E1)

 64 bit wide buses clocked at

850 MHz (1700 mbps)

 Three 72Mbit QDRII+ SRAMs

(CY7C25652KV18-500BZXC)

 36 bit wide buses clocked at

500 MHz (1000 mbps)

Storage

 Two SATA III ports (6 gbps via GTH

transceivers)

 Micro-SD Card Slot

 Two 512Mbit Micron StrataFlash parallel flash

modules (PC28F512G18A)

 For bitfile storage only

Communication Interfaces

 PCI-E Gen3 x8 supporting 8Gbps/lane

 Four SFP+ interfaces supporting 10Gbps

 Four globally unique MAC addresses

 USB-UART

 I2C Pmod Connector

Expansion Connectors

 QTH Connector (8 GTH transceivers)

 One HPC FMC Connector (10 GTH transceivers

and 68 User I/Os)

 One 12-pin Pmod Connector (8 User I/Os)

Programming

 Micro USB Connector for JTAG programming and

debugging (shared with USB-UART interface)

 Xilinx CPLD XC2C512 for FPGA configuration from

parallel flash

Power Management

 Two Linear Technology Power System Managers

(LTC2974)

 Provide current measuring on all major

power rails

Other Features

 User LEDs and Push Buttons

 PROG Push Button for manual FPGA Reset

 FPGA Configuration LEDs

 I2C Mux (PCA9548A) for controlling all onboard

I2C buses

The NetFPGA-SUME board.

Features include:

Summary of content (18 pages)

PAGE 1
300 Henley Court Pullman, WA 99163 509.334.6306 www.digilentinc.com NetFPGA-SUME™ Reference Manual Revised April 6, 2015 This manual applies to the NetFPGA-SUME rev. C Overview Powered by Xilinx's Virtex-7 XC7V690T FPGA, the NetFPGA-SUME is an ideal platform for high-performance and high-density networking design.
PAGE 2
NetFPGA-SUME™ Reference Manual Figure 1. NetFPGA-SUME component callouts. The NetFPGA-SUME is compatible with Xilinx's new high-performance Vivado® Design Suite as well as the ISE® toolset, which includes ChipScope™ and EDK. The Virtex-7 XC7V690T FPGA is not a WebPack device, which means full licenses will need to be acquired for these tools in order to build designs that target the NetFPGA-SUME. Licensing information for Vivado can be found here.
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NetFPGA-SUME™ Reference Manual FIgure 2. NetFPGA-SUME block diagram. 1 NetFPGA Organization This board is supported by reference designs and IP created by the NetFPGA organization. For more information on the NetFPGA organization, go here. 2 Power 2.1 Input Supply The NetFPGA-SUME receives power via a 2 x 4 pin PCI Express Auxiliary Power Connector.
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NetFPGA-SUME™ Reference Manual pins 15 and 16 of the main 20 pin connector of the standard ATX power supply must be shorted together, as shown in Figure 3. If these pins aren't shorted together then the power supply will not turn on. Figure 3. Pin 15 and 16 of Standard ATX power supply shorted together. According to Revision 1.
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NetFPGA-SUME™ Reference Manual Supply Rail Nominal Voltage Rated Output Current VCC1V0 1.0V 40A VCC1V8 1.8V 15A VCC2V0 2.0V 2A MGTAVCC 1.0V 8A MGTAVTT 1.2V 3A VCC3V3 3.3V 15A VCC1V5 1.5V 15A MGTVAUX 1.8V 1A DDRVTT 0.75V +/- 3A QDRVTT 0.75V +/- 3A Table 1. Supply rails, voltages, and currents.
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NetFPGA-SUME™ Reference Manual Figure 6. Regulator topology. 2.3 Power Sequencing and Supervising The components on the NetFPGA-SUME require that the supply voltages be sequenced on and off in a particular order. The NetFPGA-SUME utilizes two Linear Technology LTC2974s to ensure that these sequencing requirements are met.
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NetFPGA-SUME™ Reference Manual Additionally, the LTC2974 can margin and trim up to four output voltages using a 10-bit DAC, allowing for more precise output voltages. Figure 7. LTC2974 sequencer and supervisor. Figure 7 depicts the connections between the two LTC2974s, as well as the signals that are used to control the power on and off sequence. When the input voltage (VCC12V0) exceeds 10 volts, the LTC2974s will perform a power on sequence when the power switch (SW1) is placed in the "ON" position.
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NetFPGA-SUME™ Reference Manual When the input voltage falls below 9 volts, or the power switch transitions to the "OFF" position, the LTC2974s perform a time-based off sequence and the rails come down in the following order: 1. 2. 3. 4. 5. 6. 7. 8. MGTVAUX VCC1V5, QDRVTT, and DDRVTT VCC3V3 MGTAVTT MGTAVCC VCC2V0 VCC1V8 VCC1V0 Figure 8. Power ON/OFF sequence. The LTC2974s constantly monitor the output voltage, current, and temperature associated with each channel (supply rail).
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NetFPGA-SUME™ Reference Manual Note: the DDRVTT and QDRVTT rails are not directly monitored by the LTC2974s. Supply Rail Undercurrent Fault Limit Rated Current Overcurrent Warning Limit Overcurrent Fault Limit VCC1V0 -1A 40A 40A 44A VCC1V8 -2A 15A 15A 15.5A VCC2V0 -1A 2A 2A 3A MGTAVCC -1A 8A 8A 8.5A MGTAVTT -1A 3A 3A 3.1992A VCC3V3 -1A 15A 15A 15.5A VCC1V5 -1A 15A 15A 15.5A MGTVAUX -1A 1A 1A 1.0996A DDRVTT N/A 3A N/A N/A QDRVTT N/A 3A N/A N/A Table 3.
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NetFPGA-SUME™ Reference Manual The AUXFAULTB pins of the two LTC2974s are connected in a wire-and fashion to the cathode of a Shottky diode via the AUXFAULT net, as shown in Fig. 10. The anode of the Shottky diode is connected to pin M41 on the FPGA via the PCON_AUXFAULT_B net and protects the FPGA pin from high voltages.
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NetFPGA-SUME™ Reference Manual 2.5 Power Consumption The power consumed by the NetFPGA-SUME is largely dependent on the number of resources utilized by a given design, and the complexity of that design. This makes estimating power consumption for any particular application difficult. However, during the design process it was necessary to estimate the worst case scenario power consumption for each of the supply rails and to come up with a total power budget.
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NetFPGA-SUME™ Reference Manual 3 FPGA Configuration After power-on, the Virtex-7 FPGA must be configured (or programmed) before it can perform any functions. You can configure the FPGA in one of two ways:   A PC can use the Digilent USB-JTAG circuitry (port J16, labeled "PROG") to program the FPGA any time the power is on. One of four bitstream files stored in the parallel flash can be loaded by the onboard CPLD. Figure 12. NetFPGA-SUME configuration options.
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NetFPGA-SUME™ Reference Manual The following sections provide greater detail about programming the NetFPGA-SUME using the different methods available. 3.1 JTAG Configuration The Xilinx tools typically communicate with FPGAs using the Test Access Port and Boundary-Scan Architecture, commonly referred to as JTAG. During JTAG programming, a .
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NetFPGA-SUME™ Reference Manual  dsumecfg will not work properly if an FMC card that inserts a JTAG device into the scan chain is attached to the NetFPGA-SUME. 4 Memory 4.1 DDR3 SODIMM The NetFPGA-SUME board comes with two Micron MT8KTF51264HZ-1G9 4GB DDR3 SDRAM SODIMM, which employs an 932.84MHz 64bit-wide data bus capable of operating at a data rate of 1866MT/s. Project development with the SDRAM involves using the Xilinx Memory Interface Generator (MIG) in Vivado Design Suite.
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NetFPGA-SUME™ Reference Manual 5.2 MicroSD Card The microSD card connector on NetFPGA-SUME board provides a removable non-volatile storage resource. This connector supports a micro-SD memory card and meets all physical layer requirements of both SPI and SD bus protocols. It supports the UHS-I pin assignment standard (but not UHS-II) and provides high speed signaling at 3.3V to support SC, HC, and XC class SD cards.
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NetFPGA-SUME™ Reference Manual Virtex-7 FPGA is the master on the I2C bus, and connected to an I2C multiplexor (PCA9548) via a level shifter (FXMA2102). The PCA9548 has 8 downstream ports which are wired to SFP+ transceivers, DDR3 SODIMMs, FMC connectors, any-frequency precision clock generator (SI5324), and the PMBus (a subset of I2C protocol) interface of power management chips (LTC2974).
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NetFPGA-SUME™ Reference Manual Clock Name FPGA_SYSCLK QDRII_SYSCLK QDRIIC_SYSCLK Source IC16 DSC1103, IC17 SI5330 IC16 DSC1103, IC17 SI5330 IC16 DSC1103, IC17 SI5330 Destination Frequency Common Useage FPGA (H19, G18) 200MHz General Purpose FPGA (AD32, AD33) 200MHz Used by MIG for QDRIIA, QDRIIB FPGA (AU14, AU13) 200MHz Used by MIG for QDRIIC SATA_SYSCLK IC21 DSC1103 FPGA (MGTREFCLK0_116:T8, T7) 150MHz SFP_CLK IC20 SI5324 FPGA (MGTREFCLK0_118: E10, E9) 156.
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NetFPGA-SUME™ Reference Manual connector provides two 3.3V VCC signals (pins 6 and 12), two Ground signals (pins 5 and 11), and eight logic signals, as shown below. The VCC and Ground pins can deliver up to 1A of current. Pmod data signals are not matched pairs, and they are routed using best-available tracks without impedance control or delay matching.