DAC1006,DAC1007,DAC1008 DAC1006/DAC1007/DAC1008 P Compatible, Double-Buffered D to A Converters Literature Number: SNAS540
General Description The DAC1006/7/8 are advanced CMOS/Si-Cr 10-, 9- and 8-bit accurate multiplying DACs which are designed to interface directly with the 8080, 8048, 8085, Z-80 and other popular microprocessors. These DACs appear as a memory location or an I/O port to the µP and no interfacing logic is needed.
Absolute Maximum Ratings (Notes 1, 2) ESD Susceptibility (Note 11) Lead Temp. (Soldering, 10 seconds) Dual-In-Line Package (plastic) Dual-In-Line Package (ceramic) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.
Electrical Characteristics (Continued) = 4.75 VDC and 15.75 VDC, TA = 25˚C, VREF = 10.000 VDC unless otherwise noted Tested at VCC Parameter Conditions VCC = 12VDC ± 5% See Note Min. Output IOUT1 Capacitance IOUT2 All data inputs latched low Typ. Min. Typ. Max. 60 60 pF 250 250 pF All data inputs 250 250 pF IOUT2 latched high 60 60 pF Output Leakage TMIN≤TA≤TMAX 6 TMIN≤TA≤TMAX 6 IOUT1 All data inputs IOUT2 All data inputs latched low 0.
Electrical Characteristics (Continued) Note 10: A 200 nA leakage current with Rfb = 20K and VREF = 10V corresponds to a zero error of (200x10−9x20x103)x100÷ 10 which is 0.04% of FS. Note 11: Human body model, 100 pF discharged through a 1.5 kΩ resistor. Switching Waveforms DS005688-2 www.national.com 4 PrintDate=1998/11/17 PrintTime=11:38:08 46711 ds005688 Rev. No.
Typical Performance Characteristics Errors vs. Supply Voltage Write Width, tw Errors vs. Temperature DS005688-31 DS005688-30 DS005688-29 Control Setup Time, tCS Data Setup Time, tDS DS005688-32 Data Hold Time, tDH DS005688-34 DS005688-33 Digital Threshold vs. Supply Voltage Digital Input Threshold vs. Temperature DS005688-35 DS005688-36 5 PrintDate=1998/11/17 PrintTime=11:38:08 46711 ds005688 Rev. No. 4 www.national.
Block and Connection Diagrams DAC1006/1007/1008 (20-Pin Parts) DS005688-5 Use DAC1006/1007/1008 for left justified data. DAC1006/1007/1008 (20-Pin Parts) Dual-In-Line Package DS005688-28 Top View See Ordering Information www.national.com 6 PrintDate=1998/11/17 PrintTime=11:38:08 46711 ds005688 Rev. No.
DAC1006/1007/1008 — Simple Hookup for a “Quick Look” DS005688-7 *A TOTAL OF 10 INPUT SWITCHES & 1K RESISTORS Notes: 1. For VREF = −10.240 VDC the output voltage steps are approximately 10 mV each. 2. SW1 is a normally closed switch. While SW1 is closed, the DAC register is latched and new data can be loaded into the input latch via the 10 SW2 switches. When SW1 is momentarily opened the new data is transferred from the input latch to the DAC register and is latched when SW1 again closes.
DAC1006/1007/1008 — Simple Hookup for a “Quick Look” a. End Point Test After Zero and FS Adj. (Continued) b. Best Straight Line DS005688-37 DS005688-38 3.0 TTL COMPATIBLE LOGIC INPUTS Settling Time: Settling time is the time required from a code transition until the DAC output reaches within ± 1⁄2 LSB of the final output value. Full-scale settling time requires a zero to full-scale or full-scale to zero output change.
DAC1006/1007/1008 — Simple Hookup for a “Quick Look” (Continued) DS005688-9 FIGURE 1. Basic Logic Threshold Loop der current to the IOUT1 output pin. These MOS switches operate in the current mode with a small voltage drop across them and can therefore switch currents of either polarity. This is the basis for the 4-quadrant multiplying feature of this DAC. 4.2 Op Amp Bias Current & Input Leads The op amp bias current (IB) CAN CAUSE DC ERRORS.
DAC1006/1007/1008 — Simple Hookup for a “Quick Look” (Continued) DIGITAL INPUT CODE DS005688-39 FIGURE 2. Current Mode Switching DS005688-40 OP AMP CC pF Rj ts µS LF356 22 24 ∞ ∞ 3 LF351 LF357 10 2.4k 1.5 4 FIGURE 3. Converting IOUT to VOUT (−512≤D≤+511 or 1000000000≤D≤0111111111). If the applied digital input is interpreted as the decimal equivalent of a true binary word, VOUT can be found by: 5.1.
DAC1006/1007/1008 — Simple Hookup for a “Quick Look” (Continued) Operation is summarized in the table below: Applied 2’s Comp. 2’s Comp.
DAC1006/1007/1008 — Simple Hookup for a “Quick Look” (Continued) DS005688-43 DS005688-44 FIGURE 6. FIGURE 7. DIGITAL INPUT CODE DS005688-45 FIGURE 8. Voltage Mode Switching DS005688-46 FIGURE 9. Amplifying the Voltage Mode Output (Single Supply Operation) DS005688-47 FIGURE 10. Providing a Bipolar Output Voltage with a Single Op Amp www.national.com 12 PrintDate=1998/11/17 PrintTime=11:38:09 46711 ds005688 Rev. No.
DAC1006/1007/1008 — Simple Hookup for a “Quick Look” (Continued) DS005688-48 FIGURE 11. Increasing the Output Voltage Swing 5.4.1 Current Switching with Unipolar Output Voltage After doing a “zero adjust,” set all of the digital input levels HIGH and adjust the magnitude of VREF for The output voltage swing can be expanded by adding 2 resistors to Figure 10 as shown in Figure 11. These added resistors are used to attenuate the +V voltage.
DAC1006/1007/1008 — Simple Hookup for a “Quick Look” (Continued) DS005688-49 FIGURE 12. Full Scale Adjust — Current Switching with Bipolar Output Voltage DS005688-50 FIGURE 13. Full Scale Adjust — Voltage Switching with a Unipolar Output Voltage DS005688-15 FIGURE 14. Voltage Switching with a Bipolar Output Voltage cussed. For example, if your main interest in interfacing to a µP with an 8-bit data bus you will be directed to Section 6.1.0.
DAC1006/1007/1008 — Simple Hookup for a “Quick Look” (Continued) buffer, 2) using both digital data buffers — “double buffered,” or 3) allowing the input digital data to “flow through” to provide the analog output without the use of any data latches. on how the 2nd digital data buffer (the DAC Latch) is updated by a transfer from the 1st digital data buffer (the Input Latch).
DAC1006/1007/1008 — Simple Hookup for a “Quick Look” (Continued) DAC1006/1007/1008 (20-Pin Parts for Left Justified Data) DS005688-16 FIGURE 15. Fitting a 10-Bit Data Word into 16 Available Bit Locations DS005688-17 FIGURE 16. Input Connections and Controls for DAC1006/1007/1008 Left Justified Data www.national.com 16 PrintDate=1998/11/17 PrintTime=11:38:10 46711 ds005688 Rev. No.
DAC1006/1007/1008 — Simple Hookup for a “Quick Look” (Continued) DAC1006/1007/1008 (20–Pin Parts) 6.2.1 Automatic Transfer This makes use of a double byte (double precision) write. The first byte (8 bits) is strobed into the input latch and the second byte causes a simultaneous strobe of the two remaining bits into the input latch and also the transfer of the complete 10-bit word from the input latch to the DAC register.
DAC1006/1007/1008 — Simple Hookup for a “Quick Look” (Continued) DS005688-21 FIGURE 17. Input Connections and Logic for DAC1006/1007/1008 with 16-Bit Data Bus 6.4.1 Single Buffered Three operating modes are possible: flow through, single buffered, or double buffered. The timing diagrams for these are shown below: DAC1006/1007/1008 (20-Pin Parts) 6.3.1 Single Buffered DAC1006/1007/1008 (20-Pin Parts) DS005688-53 6.4.2 Double Buffered DAC1006/1007/1008 (20-Pin Parts) (Note 12) DS005688-51 6.3.
DAC1006/1007/1008 — Simple Hookup for a “Quick Look” (Continued) stack pointer during a PUSH allows using address bit 0 of the stack pointer as the Byte1/Byte2 and XFER strobes if bit 0 of the stack pointer address −1, (SP−1), is a “1” as presented to the DAC. Additional address decoding by the DM8131 will generate a unique DAC chip select (CS) and synchronize this CS to the two memory write strobes of the PUSH instruction.
DAC1006/1007/1008 — Simple Hookup for a “Quick Look” (Continued) for eliminating noise spikes is to add a sample and hold after the DAC op amp. This also has the advantage of eliminating noise spikes when changing digital codes. cur every time the data bus changes state. Another method DS005688-25 FIGURE 19. DAC1000 to MC6820/1 PIA Interface DS005688-55 NOTE: DATA HOLD TIME REDUCED TO THAT OF DM74LS374 (≈10 ns) FIGURE 20. Isolating Data Bus from DAC Circuitry to Eliminate Digital Noise Coupling www.
DAC1006/1007/1008 — Simple Hookup for a “Quick Look” (Continued) DS005688-56 FIGURE 21. Digitally Controlled Amplifier/Attenuator To provide a digitally controlled divider, the output op amp can be eliminated. Ground the IOUT2 pin of the DAC and VOUT is now taken from the lower op amp (which also drives the VREF input of the DAC). The expression for VOUT is now given by 7.
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Ordering Information For Left Justified Data — 20-pin package. Accuracy Temperature Range 0˚ to +70˚C 0.05% (10-bit) DAC1006LCN 0.10% (9-bit) DAC1007LCN 0.20% (8-bit) DAC1008LCN Package Outline N20A Physical Dimensions DAC1006LCWM M20B inches (millimeters) unless otherwise noted Order Number DAC1006LCWM NS Package Number M20B 23 PrintDate=1998/11/17 PrintTime=11:38:11 46711 ds005688 Rev. No. 4 www.national.
DAC1006/DAC1007/DAC1008 µP Compatible, Double-Buffered D to A Converters Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Order Number DAC1006LCN, DAC1007LCN or DAC1008LCN NS Package Number N20A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2.
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