Digital Semiconductor 21164 Alpha Microprocessor Evaluation Board User’s Guide Order Number: EC–QD2UD–TE Revision/Update Information: Digital Equipment Corporation Maynard, Massachusetts This document supersedes the Alpha 21164 Microprocessor Evaluation Board User’s Guide (EC–QD2UC–TE).
March 1996 Possession, use, or copying of the software described in this publication is authorized only pursuant to a valid written license from Digital or an authorized sublicensor. While Digital believes the information included in this publication is correct as of the date of publication, it is subject to change without notice.
Contents About This Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix 1 Introduction to the EB164 1.1 1.1.1 1.1.2 1.1.3 1.1.4 1.1.5 1.1.6 1.1.7 1.1.8 1.2 System Components and Features . . . . . . . . . . . . . . Digital Semiconductor 21171 Core Logic Chipset Memory Subsystem . . . . . . . . . . . . . . . . . . . . . . L3 Bcache Subsystem Overview . . . . . . . . . . . . . PCI Interface Overview . . . . . . . . . . . . . . . . . . . ISA Interface Overview .
3.5.3 3.5.4 3.5.5 3.6 3.7 3.8 3.9 3.10 3.11 3.11.1 3.11.2 3.11.3 3.11.4 Time-of-Year Clock . . . . . . . Utility Bus Memory Device ISA Expansion Slots . . . . . Interrupts . . . . . . . . . . . . . . . . System Clocks . . . . . . . . . . . . . Reset and Initialization . . . . . . Serial ROM . . . . . . . . . . . . . . . dc Power Distribution . . . . . . . System Software . . . . . . . . . . . Serial ROM Code . . . . . . . . Mini-Debugger Code . . . . . Debug Monitor ROM Code . Operating Systems . . . . . .
A I/O Space Address Maps A.1 PCI Sparse Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . A.2 PCI Sparse I/O Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A.2.1 PCI Sparse I/O Space—Region A . . . . . . . . . . . . . . . . . . A.2.1.1 PC87312 Combination Controller Register Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A.2.1.2 8242AH Keyboard and Mouse Controller Addresses A.2.1.3 Time-of-Year (TOY) Clock Addresses . . . . . . . . .
C Technical Support and Ordering Information C.1 C.2 C.3 C.4 Obtaining Technical Support . . . . . . . . . . . Ordering Digital Semiconductor Products . Ordering Digital Semiconductor Literature Ordering Third-Party Literature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C–1 C–1 C–3 C–4 EB164 Functional Block Diagram . . . . . . . . . . . . . . . . . EB164 Jumper Locations . . . . .
B–1 B–2 Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Special Header Content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B–6 B–9 Tables 1–1 2–1 2–2 3–1 3–2 3–3 4–1 4–2 4–3 4–4 4–5 4–6 4–7 4–8 4–9 4–10 4–11 4–12 4–13 4–14 5–1 5–2 A–1 A–2 A–3 A–4 A–5 A–6 A–7 Main Memory Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Jumper Position Descriptions . . . . . . . . . . . EB164 Connector Descriptions . . . . . . . . . . . . . .
A–8 A–9 A–10 A–11 A–12 A–13 A–14 A–15 A–16 B–1 B–2 B–3 B–4 B–5 B–6 viii Flash ROM Memory Addresses (Within Segment) . . . . . . . Map of Flash ROM Memory . . . . . . . . . . . . . . . . . . . . . . . . Flash ROM Configuration Registers . . . . . . . . . . . . . . . . . . Address Bits and PCI Device IDSEL Pins . . . . . . . . . . . . . SIO PCI-to-ISA Bridge Configuration Address Space Map . CIA Control, Diagnostic, and Error Registers . . . . . . . . . . CIA Memory Control Registers . . . . . . . . . . . .
About This Guide This guide describes Digital Semiconductor’s 21164 Alpha Microprocessor Evaluation Board (also called the EB164), an evaluation and development module for computing systems based on the 21164 Alpha Microprocessor and the Digital Semiconductor 21171 core logic chipset. Audience This guide is intended for system designers and others who use the EB164 to design or evaluate computer systems based on the 21164 microprocessor and 21171 chipset.
and peripheral component interconnect (PCI) and Industry Standard Architecture (ISA) devices. • Chapter 4, System Address Mapping, describes the mapping of the 40-bit processor address space into memory and I/O space addresses. • Chapter 5, Power and Environmental Requirements, describes the board power and environmental requirements, and identifies major board components.
Data Units The following data unit terminology, common within Digital, is used throughout this guide: Term Words Bytes Bits Word 1 2 16 Longword 2 4 32 Quadword 4 8 64 Octaword 8 16 128 Hexword 16 32 256 Note Notes provide additional information. Numbering All numbers are decimal or hexadecimal unless otherwise indicated. In case of ambiguity, a subscript indicates the radix of nondecimal numbers. For example, 19 is a decimal number, but 1916 and 19A are hexadecimal numbers.
– An UNPREDICTABLE result might acquire an arbitrary value subject to a few constraints. Such a result might be an arbitrary function of the input operands or of any state information that is accessible to the process in its current access mode. UNPREDICTABLE results may be unchanged from their previous values. Operations that produce UNPREDICTABLE results might also produce exceptions. – An occurrence specified as UNPREDICTABLE might happen or not based on an arbitrary choice function.
Data Field Size The term INTnn, where nn is one of 2, 4, 8, 16, 32, or 64, refers to a data field of nn contiguous NATURALLY ALIGNED bytes. For example, INT4 refers to a NATURALLY ALIGNED longword. Ranges and Extents Ranges are specified by a pair of numbers separated by two periods ( .. ) and are inclusive. For example, a range of 0..4 includes the integers 0, 1, 2, 3, and 4.
1 Introduction to the EB164 This chapter provides an overview of the EB164, its components, features, and uses. The Digital Semiconductor 21164 Alpha Microprocessor Evaluation Board (EB164) is an evaluation and development module for computing systems based on the Digital Semiconductor 21164 Alpha microprocessor and the Digital Semiconductor 21171 core logic chipset.
1.
1.1 System Components and Features 1.1.1 Digital Semiconductor 21171 Core Logic Chipset The 21164 is supported by the 21171 chipset. The chipset consists of the following two application-specific integrated circuit (ASIC) types: • One copy of the 21171-CA control, I/O interface, and address chip (CIA) provides the interface between the 21164, main memory (addressing and control), and the peripheral component interconnect (PCI) bus.
1.1 System Components and Features most cases. The Bcache size can be reconfigured through onboard hardware jumpers. As implemented in the EB164, the Bcache operates in 64-byte mode only. 1.1.4 PCI Interface Overview The EB164 PCI interface is the main I/O bus for the majority of functions (SCSI interface, graphics accelerator, and so on). The PCI interface provides a selectable PCI speed between 25 MHz and 33 MHz (based on the 21164 clock divisor).
1.1 System Components and Features A Xilinx XC17128 serial ROM (SROM) contains initial code that is loaded into the 21164 instruction cache (Icache) on power-up. A serial line interface is also provided to allow direct connection to a terminal line for debugging purposes. • Programmable array logic (PAL) devices for the following functions: One PAL for utility bus (Ubus) decoding One PAL for interrupts Two PAL devices for memory row address strobe (RAS) bank generation and buffering 1.1.
1.1 System Components and Features 1.1.8 Design Support The full database, including schematics and source files, is supplied. User documentation is also included. The database allows designers with no previous Alpha architecture experience to successfully develop a working Alpha system with minimal assistance. 1.
2 System Configuration and Connectors The EB164 uses jumpers to implement configuration parameters such as variations in backup cache (Bcache) size, access timing, and speed, as well as boot parameters. These jumpers must be configured for the user’s environment. Onboard connectors are provided for the I/O interfaces, single inline memory modules (SIMMs), and serial and parallel peripheral ports. After the module is configured, power can be applied, and the debug monitor can be run.
2.
2.
2.1 Configuration Jumpers Table 2–1 Configuration Jumper Position Descriptions Feature Jack/Jumper—Pins and Description System clock divisor J1—1/2, —3/4, —5/6, —7/8 (eb164.4) J1—1/2 (irq3) J1—3/4 (irq2) J1—5/6 (irq1) J1—7/8 (irq0) In In Out Out 3 In Out In In 4 In Out In Out 5 In Out Out In 6 In Out Out Out 7 Out In In In 8 Ratio1 Divisor 8 is used for 266 MHz (default). Out In In Out 9 Divisor 9 is used for 300 MHz.
2.1 Configuration Jumpers Table 2–1 (Cont.) Configuration Jumper Position Descriptions Feature Jack/Jumper—Pins and Description BC_SIZE<2:0> J1—11/12 (CONF4), —13/14 (CONF5), —15/16 (CONF6) (eb164.4) These jumpers allow the Bcache to emulate the sizes specified in the following table. These jumpers are changed in conjunction with the appropriate index jumpers J17, J16, and J15.
2.1 Configuration Jumpers Table 2–1 (Cont.) Configuration Jumper Position Descriptions Feature Jack/Jumper—Pins and Description BC_SPEED<2:0> J1—17/18 (CONF7), —19/20 (CONF8), —21/22 (CONF9) (eb164.4) These jumpers select the Bcache timing parameters used to compute the BC_CONFIG register value. Select the jumper configuration that matches the access time for the SRAMs being used.
2.1 Configuration Jumpers Table 2–1 (Cont.) Configuration Jumper Position Descriptions Feature Jack/Jumper—Pins and Description BOOT_OPTION J1—25/26 (CONF11) (eb164.4) This jumper selects the image to be loaded into memory from the system flash ROM. With the jumper out (bit = 1), the first image (debug monitor) is loaded. With the jumper in (bit = 0), alternate images can be loaded depending upon the value stored in TOY RAM location 0x3F. The default position for this jumper is out.
2.2 EB164 Connectors 2.2 EB164 Connectors Figure 2–3 shows the EB164 connectors and Table 2–2 describes them. Figure 2–4 provides a detail of header connector J2 (eb164.37).
2.
2.2 EB164 Connectors Table 2–2 EB164 Connector Descriptions Connector Pins Description Main Memory/Bcache SIMMS J10 72 DRAM 0 SIMM (eb164.18) J9 72 DRAM 1 SIMM (eb164.18) J8 72 DRAM 2 SIMM (eb164.18) J7 72 DRAM 3 SIMM (eb164.18) J6 72 DRAM 4 SIMM (eb164.19) J5 72 DRAM 5 SIMM (eb164.19) J4 72 DRAM 6 SIMM (eb164.19) J3 72 DRAM 7 SIMM (eb164.19) Note: To fill a 256-bit data path, all SIMM connectors J3 through J10 must be populated. J11 60 Bcache 0 SIMM (eb164.
2.2 EB164 Connectors Table 2–2 (Cont.) EB164 Connector Descriptions Connector Pins Description Mouse Connector J34 6 Mouse connector (eb164.32) National 87312 Combination Chip Connectors J33 26 Parallel port connector (eb164.27) Connects to an external 25-pin connector. J27 10 Serial communication port 1 connector (eb164.28) Note: This connector can be used as a terminal port for the debug monitor. J26 10 Serial communication port 2 connector (eb164.
2.2 EB164 Connectors Table 2–2 (Cont.) EB164 Connector Descriptions Connector Pins Description Speaker J2—19/21/23/25 — Speaker connector pins (eb164.37) Power On Indicator J2—26 1 Power on indicator pin (eb164.37) Connect LED from this pin to ground. System Halt Button J2—8/10 2 J2–12/14 2 System halt button pins (eb164.37) System Reset Button System reset button pins (eb164.37) Keyboard Lock Switch J2–18/20 2 Keyboard lock switch pins (eb164.
2.2 EB164 Connectors Table 2–2 (Cont.) EB164 Connector Descriptions Connector Pins Description Power Connectors J18 12 Board power connector (eb164.40) Pin Voltage/Signal 1 +3.3 V 2 +3.3 V 3 +3.3 V 4 Ground 5 Ground 6 Ground 7 Ground 8 Ground 9 Ground 10 +3.3 V 11 +3.3 V 12 +3.
2.2 EB164 Connectors Table 2–2 (Cont.) EB164 Connector Descriptions Connector Pins Description J29 12 Board power connector (eb164.40) Pin Voltage/Signal 1 p_dcok 2 Vdd (+5 V) 3 +12 V 4 –12 V 5 Ground 6 Ground 7 Ground 8 Ground 9 –5 V 10 Vdd (+5 V) 11 Vdd (+5 V) 12 Vdd (+5 V) Note: Power for the EB164 is provided by a user-supplied power supply. Digital does not provide this power supply. (Refer to Chapter 5 for more information.) J30 3 CPU fan power and sensor (eb164.
3 Functional Description This chapter describes the functional operation of the EB164. The description introduces the Digital Semiconductor 21171 ASIC support chipset and describes its implementation with the 21164 microprocessor, its supporting memory, and I/O devices. Figure 1–1 shows the EB164 major functional components. Information, such as bus timing and protocol, found in other data sheets and reference documentation is not duplicated.
3.1 EB164 Bcache Interface 3.1 EB164 Bcache Interface The 21164 controls the backup cache (Bcache) array (see Figure 3–1). The data bus (data<127:0>), check bus (data_check<15:0>), tag_dirty, and tag_ctl_par signals are shared with the system interface.
3.1 EB164 Bcache Interface The Bcache interface supports multiple cache sizes and access times. The cache sizes supported are: • 2MB with Alpha cache single inline memory modules (SIMMs) populated with 128K 2 8 static RAMs (SRAMs) • 2MB, 4MB, and 8MB with SIMMs populated with 512K 2 8 SRAMs SRAM speeds of 6 ns to 15 ns can be used. In most cases, wave pipelining can decrease the cache loop times by one CPU cycle.
3.2 Digital Semiconductor 21171 Chipset 3.2 Digital Semiconductor 21171 Chipset The 21171 chipset provides a cost-competitive solution for designers using the 21164 microprocessor to develop uniprocessor systems.
eb164.2 21164 * addr_bus_req adr_cmd_par cack cmd<3:0> dack fill fill_error fill_id idle_bc int4_valid<3:0> sys_res<1:0> tag_ctl_par tag_dirty victim_pending System Control* addr<39,34:4> data_check<15:0> data<127:0> 64−Bit PCI I/O Bus and Address mem_dat<287:144> mem_dat<143:0> eb164.8 sense_dis ras_h<1:0> set_sel_h<1:0> cas_h<3:0> mem_we_h<1:0> mem_addr<11:0> iod<63:0> iod_ecc<7:0> Control, I/O Interface, cmc<8:0> ioc<<6:0> mem_en eb164.10−.13 (X 4) Data Switch Buffer eb164.
3.2 Digital Semiconductor 21171 Chipset Two DMA conversion methods are supported: direct mapping, where a base offset is concatenated with the PCI address, and scatter-gather mapping, which maps an 8KB PCI page to any 8KB memory page. The CIA contains an 8-entry scatter-gather translation lookaside buffer (TLB), where each entry holds four consecutive page table entries (PTEs). Refer to Chapter 4 for additional details on PCI and DMA address mapping. 3.2.
3.3 Main Memory Interface • • • • 2 36-bit DRAM SIMM 4MB 2 36-bit DRAM SIMM 8MB 2 36-bit DRAM SIMM 16MB 2 36-bit DRAM SIMM 2MB The following memory sizes are supported with one set of eight SIMMs: • 32MB memory • 64MB memory • 128MB memory • 256MB memory • 512MB memory The row and column addresses for the DRAM SIMMs are partitioned such that any victim’s row address will match its corresponding read miss’s row address.
3.4 PCI Devices 3.4.1 Saturn-IO (SIO) Chip To provide the EB164 with greater flexibility, the only embedded PCI device is the SIO PCI-to-ISA chip. All other functions are provided by option modules. The 82378ZB SIO chip provides the bridge between the PCI bus and the Industry Standard Architecture (ISA) bus.
eb164.25 PCI−to−ISA Bridge 82378ZB PCI Bus sa<9:0> J28 J26 Com2 sa<2:0> ubus_data<0> ior,iow ecasaddr<2:0> J27 Com1 Parallel J33 Diskette J31 IDE eb164.31 Transceivers sa<19:0> eb164.27 Combination Controller 87312 sd<7:0> eb164.30 Ubus Decoder eb164.4 Config. Jumpers sd<15:0> la<23:17> adr19 sa<18:0> eb164.33 Flash ROM 1M X 8b ubus_data<7:0> eb164.33 Time−of− Year Clock DS1287 sa<2> eb164.
3.5 ISA Bus Devices 3.5.1 Combination Controller The EB164 uses the National Semiconductor PC87312 as the combination controller chip. (See Figure 3–3.) It is packaged in a 100-pin PQFP configuration. The chip provides the following ISA peripheral functions: • Integrated drive electronics (IDE) controller—Provides a complete IDE interface. Signal buffers are provided on the EB164. The interface is brought out to a standard 40-pin header. A ribbon cable connects the header to one or two IDE drives.
3.5 ISA Bus Devices 3.5.2 Keyboard and Mouse Controller The Intel N8242 located on the ISA utility bus provides the keyboard and mouse controller functions. It is packaged in a 44-pin plastic leadless chip carrier (PLCC) configuration. The 8242 is an Intel UPI™-42AH universal peripheral interface. It is an 8-bit slave microcontroller with 2KB of ROM and 256 bytes of RAM that has been preprogrammed with a keyboard BIOS for standard scan codes.
3.5 ISA Bus Devices 3.5.4 Utility Bus Memory Device The EB164 utility bus (Ubus) drives a flash ROM memory device. The flash ROM chip provides 1MB of flash memory for operating system support. Flash data is accessed through 20 address inputs. The low-order 19 address bits are driven by ISA bus sa<18:0>. The high-order 20th bit (flash_adr19) is driven by the Ubus decode PAL. Address bit flash_adr19 can be changed by writing to ISA I/O port x800.
3.6 Interrupts 3.6 Interrupts This section describes the EB164 interrupt logic. PCI-, ISA-, and CIA-generated interrupts are each described. Figure 3–4 shows the interrupt logic. The PCI-to-ISA SIO bridge chip provides the functionality of two 8259 interrupt control devices. These ISA-compatible interrupt controllers are cascaded such that 14 external and two internal interrupts are available. The PCI interrupt acknowledge command should be used to read the interrupt request vector from the SIO.
3–14 Functional Description eb164.26 eb164.32 irq<15:3 ,1> <12, 1> sio_int pci_isa_irq <7:3> eb164.27 Combination Controller Ubus<7:0> eb164.30 System Interrupt PLD Keyboard and Mouse Controller drq<7:5, 3:0> irq_reset_l ISA Bus Decodes sense_dis pci_int xn _l ISA Slots eb164.20−.22 PCI Slots PCI Bus eb164.25 PCI−to−ISA Bridge eb164.8 Control, I/O Interface, and Address eb164.
3.
3.7 System Clocks 3.7 System Clocks Figure 3–5 shows the EB164 clock generation and distribution scheme. The EB164 system includes input clocks to the microprocessor as well as clock distribution for the various system memory and I/O devices. There are other miscellaneous clocks for ISA bus support. System clocking can be divided into three main areas: • Microprocessor input clock The input clock runs at twice the operating frequency of the 21164. The EB164 supports cycle times from 3.2 ns to 5.0 ns.
3.7 System Clocks Figure 3–5 System Clocks and Distribution Socketed 26.6−MHz Oscillator Socketed PLL Clock Generator X20 eb164.3 eb164.3 clk_in_h 21164 Microprocessor clk_in_l irq_h<3:0> eb164.2 sys_clk_out1 PLL Clock Driver Loop Filter cia_clk DSW0 DSW1 DSW2 DSW3 dsw0_clk dsw1_clk dsw2_clk dsw3_clk pci0_clk pci1_clk pci2_clk pci3_clk sio_clk eb164.35 14.3−MHz Crystal CIA Frequency osc14 Generator PCI Sockets 82378 Bridge clkb sysclk clkb_l 8242 Keyboard and Mouse Controller eb164.
3.7 System Clocks At system reset, the microprocessor’s irq_h<3:0> pins are driven by the clock divisor values set by four jumpers on J1. During normal operation, these signals are used for interrupt requests. The pins are either switched to ground or pulled up in a specific combination to set the 21164’s internal divider. The divisor is programmable and can range from 3 to 15. (Refer to Table 2–1 for a list of jumper combinations.
3.8 Reset and Initialization 3.8 Reset and Initialization A TL7702B power monitor senses +3 V dc to ensure that it is stable before the 21164 CPU’s inputs and I/O pins are driven (see Figure 3–6). Any device that drives the 21164 has a tristate output controlled by the power monitor output. This is necessary because the 21164 must not have its inputs driven to greater than 4.0 V if the 3.3-V level to the 21164 is not greater than 2.5 V. The TL7702B provides this function by sensing whether the 3.
3–20 Functional Description Power Supply Reset Switch Fan Sensor +3 V J18 1 eb164.40 J29 16 14 eb164.37 J2 2 eb164.40 J30 eb164.40 p_dcok Debounce fan_ok_l eb164.38 Power Sense sense_dis b_dcok pre_reset_h rst1_l rst_l eb164.38 cpu_dcok cpu_reset_l Buffering sys_reset(n)_l MK−2306−16 eb164.2 21164 To: DSWs SIO irq PLA Flash ROM irq Multiplexer eb164.8 CIA To: Arbiter RAS PLAs Bcache Buffer 3.
3.9 Serial ROM 3.
3.10 dc Power Distribution Figure 3–7 SROM and Serial Port srom_dat 21164 srom_oe_l SROM real_srom_d PLD MUX srom_clk eb164.2 2 5 eb164.4 eb164.30 srom_clk_l test_srom_d test_srom_d_l J13 eb164.28 eb164.4 MK−2306−17 3.10 dc Power Distribution The EB164 derives its system power from a user-supplied PC power supply. The power supply must provide +12 V dc and –12 V dc, –5 V dc, +3 V dc, and Vdd (+5 V dc). The dc power is supplied through power connectors J18 and J29 (eb164.40).
12 11 10 9 8 7 6 5 4 3 2 1 J18 12 11 10 9 8 7 6 5 4 3 2 J29 eb164.40 Power Connectors +3 V eb164.26 ISA Conn. GND (Vss) −5 V +12 V −12 V Vdd eb164.22 PCI32 Conn. Spkr +3 V Pull−Ups Pull−Downs +5 V Pull−Ups Integrated Circuits/Clocks Flash ROM Fan MK−2306−25 eb164.2 21164 P/J30 Fans (J1) 3.
3.11 System Software 3.11 System Software EB164 software consists of the following: • Serial ROM code • Mini-Debugger code • Debug monitor ROM code • Windows NT ARC firmware • Operating systems The serial ROM code, Mini-Debugger code, debug monitor code, and Windows NT ARC firmware are all included with the EB164 and do not require a license. Only binaries for the Windows NT ARC firmware are included, not the sources. Operating systems are available as licensed products.
3.11 System Software For additional information, refer to the Alpha Microprocessors SROM MiniDebugger User’s Guide. 3.11.3 Debug Monitor ROM Code The EB164 includes a flash ROM that contains the debug monitor code. Room is provided in this ROM for user-specific code development. This code can be loaded independently. The user can develop code on a host system, then load the code into the EB164 system through an Ethernet board or diskette.
4 System Address Mapping This chapter describes the mapping of the 40-bit processor physical address space into cacheable and noncacheable memory addresses, the translation of the processor-initiated address into a peripheral component interconnect (PCI) space address, and the translation of PCI-initiated addresses into system memory addresses. 4.
4.1 Physical Memory Regions Table 4–1 Three Physical Memory Regions Region Address Range16 Description Cacheable 00.0000.0000–7F.FFFF.FFFF Write-back cached, load and store merging operations permitted, 64-byte transfers. Noncacheable 80.0000.0000–FF.FFEF.FFFF Not cached, load-merging operations limited, storemerging operations permitted, 32-byte transfers. Cbox IPR region FF.FFF0.0000–FF.FFFF.FFFF Cbox IPRs.
4.1 Physical Memory Regions Table 4–2 Physical Memory Regions (Detailed) Region16 Description 00.0000.0000–00.3FFF.FFFF Cacheable memory space (1GB) 00.4000.0000–7F.FFFF.FFFF UNDEFINED space (511GB) 80.0000.0000–83.FFFF.FFFF PCI sparse memory space—region 0 (16GB through 512MB) 84.0000.0000–84.FFFF.FFFF PCI sparse memory space—region 1 (4GB through 128MB) 85.0000.0000–85.7FFF.FFFF PCI sparse memory space—region 2 (2GB through 64MB) 85.8000.0000–85.BFFF.
4.1 Physical Memory Regions Caution Due to CIA chip pin constraints, CPU address bits <38:35> are not brought onchip. Software must ensure that CPU address bits <38:35> are always zero (to ensure even parity). Otherwise, the CIA chip will generate parity error interrupts during address cycles. 4.2 21164 Address Mapping to PCI Space The control, I/O interface, and address chip (CIA) generates 32-bit PCI addresses but accepts both 64-bit address (DAC 1 ) cycles and 32-bit PCI address (SAC 2 ) cycles.
4.2 21164 Address Mapping to PCI Space 4.2.1 Cacheable Memory Space (00.0000.0000 Through 00.3FFF.FFFF) The EB164 recognizes the first 1GB of the physical address space to be cacheable memory space. It responds to all read and write accesses in this space. The block size is fixed at 64 bytes. The EB164 uses a read/flush-based cache coherence protocol. All DMA read accesses are sent to the 21164 as read probes while all DMA write accesses are sent to the 21164 as flush probes.
4.2 21164 Address Mapping to PCI Space • Software must use longword load or store instructions (LDL/STL) to perform a reference that is of longword length (or less) on the PCI. The bytes to be transferred must be positioned within the longword in the correct byte lanes as indicated by the PCI byte enables. The EB164 performs no byte shifting within the longword. Quadword load and store instructions must only be used to perform a quadword transfer.
4.
4.2 21164 Address Mapping to PCI Space PCI address bits <31:26> are obtained from either the hardware extension register (HAE_MEM), or the CPU address, depending upon the sparse space being accessed. This is shown in Table 4–5. HAE_MEM is a CSR in the CIA chip and is described in Section A.6.1.
4.
4.2 21164 Address Mapping to PCI Space to address a 32MB region that can be relocated by using the HAE_IO register located in the CIA chip. 4.2.4 PCI Sparse I/O Space (85.8000.0000 Through 85.FFFF.FFFF) PCI sparse I/O space is sparse and has characteristics similar to the PCI sparse memory space. This 2GB physical address space maps to two 32MB regions of PCI I/O address space. A read or write operation to this space causes a PCI I/O read or PCI I/O write command, respectively.
4.
4.
4.2 21164 Address Mapping to PCI Space 4.2.5 PCI Dense Memory Space (86.0000.0000 Through 86.FFFF.FFFF) PCI dense memory space is typically used for PCI data buffers (such as a video frame buffer) and has the following characteristics: • There is one-to-one mapping between CPU addresses and PCI addresses. A longword address from the CPU maps to a longword address on the PCI. Hence, the name dense space (as opposed to PCI sparse memory space). • Byte or word accesses are not permitted in this space.
4.2 21164 Address Mapping to PCI Space Note If the data written by the processor has holes, that is, some of the longwords have been masked out, the corresponding transfer will still be performed on the PCI bus with disabled byte-enables. Downstream bridges must be able to deal with disabled byte-enables on the PCI bus during write transactions.
4.2 21164 Address Mapping to PCI Space There are two classes of targets for PCI configuration read and write commands: devices on the primary PCI bus and peripherals on hierarchical (buffered, secondary) PCI buses, which are accessed through bridge chips. Address usage during PCI configuration cycles varies depending on the intended target of the configuration cycle.
4.2 21164 Address Mapping to PCI Space Table 4–7 PCI Configuration Space Definition Bus Hierarchy PCI_AD Bits Definition Local <31:24> Forced to 0 by the CIA chip. <23:11> Can be used for IDSEL or ignored. Typically, the IDSEL pin of each PCI device is connected to a different address line. This requires that only one bit of this field be asserted in a given cycle. <10:8> Function select (1 of 8). <7:2> Register select. <1:0> 00 <31:24> Ignored—forced to 0 by the CIA chip.
4.
4.
4.2 21164 Address Mapping to PCI Space Table 4–10 EB164 Primary PCI IDSEL Mapping IDSEL Device PCI Address Bit Physical Address PCI slot 2 pci_ad<16> 87.0005.0000 PCI slot 0 pci_ad<17> 87.0006.0000 PCI slot 1 pci_ad<18> 87.0007.0000 PCI-to-ISA SIO bridge pci_ad<19> 87.0008.0000 PCI slot 3 pci_ad<20> 87.0009.0000 4.2.7 PCI Interrupt Acknowledge/Special Cycle Space (87.2000.0000 Through 87.3FFF.FFFF) The special cycle command provides a simple message broadcasting mechanism on the PCI.
4.2 21164 Address Mapping to PCI Space Table 4–11 Hardware-Specific Register Space CPU Address <39:28> Selected Region CPU Address <27:6> CPU Address <5:0> 1000 0111 0100 CIA control, diagnostic, error registers LW address 00 0000 1000 0111 0101 CIA memory control registers LW address 00 0000 1000 0111 0110 CIA PCI address translation LW address 00 0000 1000 0111 0111 Reserved — — 1000 0111 1xxx Reserved — — 4.2.
4.
4.2 21164 Address Mapping to PCI Space Note The window base addresses should be on NATURALLY ALIGNED address boundaries, depending on the size of the window.
4.
4.
4.
4.2 21164 Address Mapping to PCI Space An 8-entry translation-lookaside buffer (TLB) is provided in the CIA chip for scatter-gather map entries. The TLB is a fully associative cache and holds the eight most recent scatter-gather map lookups. Four of these entries can be ‘‘locked,’’ thus preventing their displacement by the hardware TLB-miss handler. Each of the eight TLB entries holds a PCI address for the tag, and four consecutive 8KB CPU page addresses as the TLB data.
4.2 21164 Address Mapping to PCI Space 2. Bits <20:1> of the map entry (PTE) are used to generate the physical page address. This address is appended to the page offset to generate the physical memory address. The TLB is also updated with the four PTE entries that correspond to the 32KB PCI page address, which first missed the TLB. The tag portion of the TLB is loaded with this PCI page address, and the DAC bit is set if the PCI cycle was a DAC cycle. 3.
5 Power and Environmental Requirements This chapter describes the evaluation board power and environmental requirements, and physical board parameters. 5.1 Power Requirements The EB164 derives its main dc power from a user-supplied power supply. The board has a total power dissipation of 116 W, excluding any plug-in PCI and ISA devices. Table 5–1 lists the power requirement for each dc supply voltage. The power supply must supply a dcok signal to the system reset logic. Refer to Section 3.
5.2 Environmental Requirements 5.2 Environmental Requirements The 21164 microprocessor is cooled by a small fan blowing directly into the chip’s heat sink. The EB164 motherboard is designed to run efficiently using only this fan. Additional fans may be necessary depending upon cabinetry and I/O board requirements.
5.3 Physical Board Parameters Figure 5–1 Board Component Layout 33.15 cm (13.05 in) 1 1 7 1 8 3 4 6 5 9 2 10 30.73 cm (12.
5.3 Physical Board Parameters Table 5–2 Board Component List Locator Number Component Number Component Description 1 U42 Digital Semiconductor 21164 Alpha microprocessor (eb164.2) 2 U41 21171-CA control, I/O interface, and address (CIA) chip (eb164.8) 3 U32 21171-BA data switch (DSW0) chip (eb164.10) 4 U15 21171-BA data switch (DSW2) chip (eb164.12) 5 U10 21171-BA data switch (DSW1) chip (eb164.11) 6 U2 21171-BA data switch (DSW3) chip (eb164.
A I/O Space Address Maps This appendix provides lists of the physical EB164 I/O space assignments, including CIA operating register address space maps and PCI/ISA device register maps. Refer to Chapter 4 for detailed information on sparse/dense space and address translation. The lists include only that portion that is unique to EB164 and that affects or reflects the system environment.
A.2 PCI Sparse I/O Space A.2.1 PCI Sparse I/O Space—Region A PCI sparse I/O space—region A—occupies physical addresses 85.8000.0000 through 85.BFFF.FFFF. The ISA devices are included in this space. Sections A.2.1.1 through A.2.1.4 list the ISA device address maps. A.2.1.1 PC87312 Combination Controller Register Address Space Table A–1 lists the base address values for the PC87312 combination integrated drive electronics (IDE), diskette, serial port, and parallel port controller.
A.2 PCI Sparse I/O Space Table A–1 (Cont.) PC87312 Combination Controller Register Address Space Map Address Offset Read/Write Physical Address Register 1F0-R/W 85.8000.3E00 Data 1F1-R 85.8000.3E20 Error 1F1-W 85.8000.3E20 Features (write precomp) 1F2-R/W 85.8000.3E40 Sector count 1F3-R/W 85.8000.3E60 Sector number 1F4-R/W 85.8000.3E80 Cylinder low 1F5-R/W 85.8000.3EA0 Cylinder high 1F6-R/W 85.8000.3EC0 Drive/head 1F7-R 85.8000.3EE0 Status 1F7-W 85.8000.
A.2 PCI Sparse I/O Space Table A–1 (Cont.) PC87312 Combination Controller Register Address Space Map Address Offset Read/Write Physical Address Register COM2 Serial Port Registers 2F8-R 0DLAB=0 85.8000.5F00 COM2 receiver buffer 2F8-W 0DLAB=0 85.8000.5F00 COM2 transmitter holding 2F8 0DLAB=1 85.8000.5F00 COM2 divisor latch (LSB) 2F9 1DLAB=0 85.8000.5F20 COM2 interrupt enable 2F9 1DLAB=1 85.8000.5F20 COM2 divisor latch (MSB) 2FA-R 85.8000.5F40 COM2 interrupt identification 2FA-W 85.
A.2 PCI Sparse I/O Space Table A–1 (Cont.) PC87312 Combination Controller Register Address Space Map Address Offset Read/Write Physical Address Register 3F0-R 85.8000.7E00 Status A 3F1-R 85.8000.7E20 Status B 3F2-R/W 85.8000.7E40 Digital output 3F3-R/W 85.8000.7E60 Tape drive 3F4-R 85.8000.7E80 Main status 3F4-W 85.8000.7E80 Data rate select 3F5-R/W 85.8000.7EA0 Data (FIFO) 3F6 85.8000.7EC0 None (tristate bus) 3F7-R 85.8000.7EE0 Digital input 3F7-W 85.8000.
A.2 PCI Sparse I/O Space A.2.1.2 8242AH Keyboard and Mouse Controller Addresses Table A–2 lists the register and memory addresses for the keyboard/mouse controller. Table A–2 Keyboard and Mouse Controller Addresses Offset Physical Address Register 60-R 85.8000.0C00 Auxiliary/keyboard data 60-W 85.8000.0C00 Command data 64-R 85.8000.0C80 Read status 64-W 85.8000.0C80 Command A.2.1.3 Time-of-Year (TOY) Clock Addresses Table A–3 lists the register and memory addresses for the TOY clock device.
A.2 PCI Sparse I/O Space Table A–3 Time-of-Year Clock Device Addresses Offset Latched Index Physical Address Register 70 0 85.8000.0E00 Seconds 70 1 85.8000.0E00 Seconds alarm 70 2 85.8000.0E00 Minutes 70 3 85.8000.0E00 Minutes alarm 70 4 85.8000.0E00 Hour 70 5 85.8000.0E00 Hour alarm 70 6 85.8000.0E00 Day of week 70 7 85.8000.0E00 Day of month 70 8 85.8000.0E00 Month 70 9 85.8000.0E00 Year 70 A 85.8000.0E00 Register A 70 B 85.8000.
A.2 PCI Sparse I/O Space A.2.1.5 Configuration Jumpers (CONF4—CONF15) Reading the addresses listed in Table A–5 returns the value of the configuration jumpers CONF4 through CONF15. Bits corresponding to CONF0 through CONF3 are hardwired to the presence detect signals from the DRAM SIMMs. Table A–5 Configuration Jumpers (CONF4—CONF15) Offset Physical Address Description x801 85.8001.0020 Bits <3:0> are presence detect signals . Bits <7:4> are CONF<7:4>. x802 85.8001.
A.2 PCI Sparse I/O Space Table A–7 SIO PCI-to-ISA Bridge Operating Register Address Space Map Offset Address Register 000 85.C000.0000 DMA1 CH0 Base and Current Address 001 85.C000.0020 DMA1 CH0 Base and Current Count 002 85.C000.0040 DMA1 CH1 Base and Current Address 003 85.C000.0060 DMA1 CH1 Base and Current Count 004 85.C000.0080 DMA1 CH2 Base and Current Address 005 85.C000.00A0 DMA1 CH2 Base and Current Count 006 85.C000.00C0 DMA1 CH3 Base and Current Address 007 85.C000.
A.2 PCI Sparse I/O Space Table A–7 (Cont.) SIO PCI-to-ISA Bridge Operating Register Address Space Map Offset Address Register 083 85.C000.1060 DMA Channel 1 Page 084 85.C000.1080 DMA Page Register Reserved 085 85.C000.10A0 DMA Page Register Reserved 086 85.C000.10C0 DMA Page Register Reserved 087 85.C000.10E0 DMA Channel 0 Page 088 85.C000.1100 DMA Page Register Reserved 089 85.C000.1120 DMA Channel 6 Page 08A 85.C000.1140 DMA Channel 7 Page 08B 85.C000.
A.2 PCI Sparse I/O Space Table A–7 (Cont.) SIO PCI-to-ISA Bridge Operating Register Address Space Map Offset Address Register 0C6 85.C000.18C0 DMA2 CH1 Base and Current Count 0C8 85.C000.1900 DMA2 CH2 Base and Current Address 0CA 85.C000.1940 DMA2 CH2 Base and Current Count 0CC 85.C000.1980 DMA2 CH3 Base and Current Address 0CE 85.C000.19C0 DMA2 CH3 Base and Current Count 0D0 85.C000.1A00 DMA2 Status(r) and Command(w) 0D2 85.C000.1A40 DMA2 Write Request 0D4 85.C000.
A.2 PCI Sparse I/O Space Table A–7 (Cont.) SIO PCI-to-ISA Bridge Operating Register Address Space Map Offset Address Register 41B 85.C000.8360 CH3 Scatter/Gather Status 41D 85.C000.83A0 CH5 Scatter/Gather Status 41E 85.C000.83C0 CH6 Scatter/Gather Status 41F 85.C000.83E0 CH7 Scatter/Gather Status 420–423 85.C000.8418 CH0 Scatter/Gather Descriptor Table Pointer 424–427 85.C000.8498 CH1 Scatter/Gather Descriptor Table Pointer 428–42B 85.C000.
A.3 PCI Dense Memory Space A.3 PCI Dense Memory Space PCI dense memory space occupies physical addresses 86.0000.0000 through 86.FFFF.FFFF and is typically used for PCI data buffers (such as a video frame buffer). Refer to Section 4.2.5 for additional information. A.3.1 Flash ROM Memory Addresses Table A–8 lists the address range for the flash ROM. Refer to Section A.2.1.4 for details on selecting one of two flash ROM segments.
A.3 PCI Dense Memory Space A.3.3 Flash ROM Configuration Registers Table A–10 lists the configuration registers for the Intel 28F008SA 1MB flash ROM. A read operation is performed by reading from the appropriate address. To write data, the flash ROM must first be erased. The structure of the flash ROM allows only the flash ROM to be erased in 64KB blocks (see Section A.3.2). In order to change one byte, the following steps must be completed: 1. Read the entire 64KB block into system memory. 2.
A.3 PCI Dense Memory Space Table A–10 Flash ROM Configuration Registers Offset Data Written on First Access Register X1 FF Read array/reset register X 90 Intelligent identifier register X 70 Read status register 50 Clear status register 20 Erase setup/confirm register X B0 Erase suspend/resume register WA3 40 Byte write setup/write register WA 10 Alternate byte write setup/write register X BA 1X 2 = Any byte within the flash ROM address range.
A.4 PCI Configuration Address Space A.4 PCI Configuration Address Space The PCI configuration address space occupies physical addresses 87.0000.0000 through 87.1FFF.FFFF. The PCI configuration register set occupies this space. A read or write access to this space causes a configuration read or write cycle on the PCI. Table A–11 identifies the EB164 PCI devices and the corresponding PCI address bit that drives the device’s IDSEL pin. Refer to Section 4.2.6 for additional information on this space.
A.4 PCI Configuration Address Space Table A–12 SIO PCI-to-ISA Bridge Configuration Address Space Map Offset Address Register 00–01 87.0008.0008 Vendor ID 02–03 87.0008.0048 Device ID 04–05 87.0008.0088 Command 06–07 87.0008.00C8 Device Status 08 87.0008.0100 Revision ID 40 87.0008.0800 PCI Control 41 87.0008.0820 PCI Arbiter Control 42 87.0008.0840 PCI Arbiter Priority Control 44 87.0008.0880 MEMCS# Control 45 87.0008.08A0 MEMCS# Bottom of Hole 46 87.0008.
A.5 PCI Interrupt Acknowledge/Special Cycle Address Space A.5 PCI Interrupt Acknowledge/Special Cycle Address Space This space occupies physical addresses 87.2000.0000 through 87.3FFF.FFFF. Refer to Section 4.2.7 for additional information. A.6 Hardware-Specific and Miscellaneous Register Space This space occupies physical addresses 87.4000.0000 through 87.6FFF.FFFF and covers the 21171-CA (CIA) address space. Registers accessed in this space use a hardware-specific variant of sparse space encoding.
A.6 Hardware-Specific and Miscellaneous Register Space Table A–13 (Cont.) CIA Control, Diagnostic, and Error Registers Register Type Address Description CPU_ERR1 RO 87.4000.8040 CPU error information register 1 CIA_ERR R/WC 87.4000.8200 CIA error register CIA_STAT RW 87.4000.8240 CIA status register ERR_MASK R/WC 87.4000.8280 CIA error mask register CIA_SYN RO 87.4000.8300 CIA syndrome register CIA_MEM0 RO 87.4000.8400 CIA memory port status register 0 CIA_MEM1 RO 87.4000.
A.6 Hardware-Specific and Miscellaneous Register Space A.6.3 CIA PCI Address Translation Map Space CIA PCI address translation map space occupies physical addresses 87.6000.0000 through 87.6FFF.FFFF. Table A–15 lists all the CIA chip’s PCI address translation registers. Table A–15 PCI Address Translation Registers Register Type Address Description TBIA WO 87.6000.0100 Scatter-gather translation buffer invalidate register W0_BASE RW 87.6000.0400 Window base 0 register W0_MASK RW 87.6000.
A.6 Hardware-Specific and Miscellaneous Register Space Table A–15 (Cont.) PCI Address Translation Registers Register Type Address Description TB0_PAGE2 RW 87.6000.1080 Translation buffer 0 page2 TB0_PAGE3 RW 87.6000.10C0 Translation buffer 0 page3 TB1_PAGE0 RW 87.6000.1100 Translation buffer 1 page0 TB1_PAGE1 RW 87.6000.1140 Translation buffer 1 page1 TB1_PAGE2 RW 87.6000.1180 Translation buffer 1 page2 TB1_PAGE3 RW 87.6000.11C0 Translation buffer 1 page3 TB2_PAGE0 RW 87.6000.
A.6 Hardware-Specific and Miscellaneous Register Space Table A–15 (Cont.) PCI Address Translation Registers Register Type Address Description TB7_PAGE3 RW 87.6000.17C0 Translation buffer 7 page3 A.7 21164 Alpha Microprocessor Cbox IPR Space The 21164 microprocessor cache control and bus interface unit (Cbox) IPR space occupies physical addresses FF.FFF0.0000 through FF.FFFF.FFFF.
B SROM Initialization The 21164 Alpha microprocessor provides a mechanism for loading the initial instruction stream (Istream) from a compact serial ROM (SROM) to start the bootstrap procedure. The SROM executable image is limited to the size of the CPU instruction cache (Icache). Because the image is running only in the Icache, it is relatively difficult to debug.
B.1 SROM Initialization 9. Scan the system flash ROM for a special header that specifies where and how the system flash ROM firmware should be loaded. 10. Copy the contents of the system flash ROM to memory and begin code execution. 11. Pass parameters up to the next level of firmware to provide a predictable firmware interface. B.2 Firmware Interface A firmware interface provides a mechanism for passing critical information about the state of the system and CPU up to the next level of firmware.
B.2 Firmware Interface Table B–1 (Cont.) Output Parameter Descriptions Output Parameter Parameter Description r18 (a2)—Cycle count in picoseconds This value is the number of picoseconds that elapse for each increment of the processor cycle count (as read by the RPCC instruction).
B.2 Firmware Interface Table B–1 (Cont.) Output Parameter Descriptions Output Parameter Parameter Description r21 (a5)—System context value The context value is interpreted in a system-specific manner. If the system needs to pass more than one system-specific parameter, then it may pass a context value. A context value is a physical address pointer to a data structure of many system-specific values. B.3 Automatic CPU Speed Detection The EB164 real-time clock (RTC) detects the speed of the CPU.
B.4 CPU Bus Interface Timing Table B–3 Typical SRAM Specifications Function Description Toe Access from OE valid to data valid Twc Write cycle time Twp Write pulse width Tdw Data setup to write pulse deassertion Tdh Data hold from write pulse deassertion Taw Address setup to write pulse deassertion Twr Address hold from write pulse deassertion Tas Address setup to write pulse assertion Table B–4 CPU Specifications Function Description Taod data_ram_oe_h output delay.
B.5 Bcache Read and Write Timing Calculations B.5 Bcache Read and Write Timing Calculations The following sections describe methods of calculating read and write cycle times. B.5.1 Read Cycle Calculation In the 21164, after a Bcache read command begins on CPU cycle N, at time T, there will be a driver delay Tdd that will slow down the signal and cause it to appear at the pins at time T + Tdd. There will also be some clock skew of 0.4 ns, delaying some signals until time T + Tdd + 0.4 ns.
B.5 Bcache Read and Write Timing Calculations Once the index signals have reached the SRAMs and the write-enable has been asserted, it must be determined when the write-enable signal can be deasserted. This is done by computing how much time it takes to perform the write operation, assuming the data is already present. This is WRsetup + Taw, where Taw is the amount of time required by the SRAM to write the data.
B.5 Bcache Read and Write Timing Calculations B.5.3 Read/Write Spacing Calculations The 21164 uses the RD_WR_SPC field as the number of CPU cycles to insert between a private read operation followed by a private write operation. The number should be large enough to allow the Bcache drivers to turn off before the 21164 data drivers are turned on, thus avoiding a data bus clash. To compute this value, the worst case delay of data_ram_oe_h signal needs to be determined.
B.8 Special ROM Header B.8 Special ROM Header The MAKEROM tool is used to place a special header on ROM image files. The SROM allows the system (flash) ROM to contain several different ROM images, each with its own header. The header informs the SROM where to load the image, and whether or not it has been compressed with the MAKEROM tool. The header is optional for system ROMs containing a single image.
B.8 Special ROM Header Table B–5 describes each entry in the special header. Table B–5 Special Header Entry Descriptions Entry Description Validation and inverse validation pattern This quadword contains a special signature pattern used to validate that the special ROM header has been located. The pattern is 5A5AC3C3A5A53C3C. Header size (bytes) This longword provides the size of the header block, which varies among versions of the header specification.
B.8 Special ROM Header Table B–5 (Cont.) Special Header Entry Descriptions Entry Description Firmware ID The firmware ID is a byte that specifies the firmware type. This information facilitates image boot options necessary to boot different operating systems.
B.9 Flash ROM Structure B.9 Flash ROM Structure During the power-up and initialization sequence, the EB164 always loads the first image if BOOT_OPTION=1 (jumper J1—25/26 not installed). Then the first image (the debug monitor) will be booted. If jumper J1—25/26 (BOOT_OPTION) is installed (see Figure 2–2), the EB164 reads the value at location 0x3F of the TOY RAM. The EB164 uses the value found there to determine which image will be selected (see Table B–6). The selected image is loaded and executed.
B.9 Flash ROM Structure Changing TOY RAM Location 3F—Basic Debug Monitor Commands Follow this procedure to change the value in location 0x3F, then load and start the selected image: 1. Remove the jumper at J1—25/26 (BOOT_OPTION) (see Figure 2–2). 2. Turn power on. The debug monitor will be loaded. 3. Determine the TOY RAM value for the image you have chosen. 4. Use the debug monitor to write nn (selected operating system type from Table B–6) in TOY RAM location 0x3F.
B.9 Flash ROM Structure Changing TOY RAM Location 0x3F—Debug Monitor bootopt Command Use the debug monitor bootopt command to change the value in location 3F. In the example shown here, the bootopt command is used to change the value in location 3F from 0 to 1. EB164> bootopt ! Predefined bootoptions are... "0" "Alpha Evaluation Board Debug Monitor" "DBM" "1" "The Windows NT Operating System" "NT" "2" "OpenVMS" "VMS" "3" "Digital UNIX" "UNIX" O/S type selected: "Alpha Evaluation Board Debug Monitor" ....
B.10 Flash ROM Access B.10 Flash ROM Access The flash ROM can be viewed as two banks of 512KB each. At power-up the lower 512KB bank is accessed using the address range 86.FFF8.0000 to 86.FFFF.FFFF. Setting address bit 19 (flash_adr19) allows you to access the higher 512KB of flash ROM. Write a 1 to the register at address 0x800 to set address bit 19. Manually deposit a 1 to address 0x800 or enter the following command from the debug monitor: > wb 800 1 The address range for the higher bank is 86.FFF8.
B.11 Icache Flush Code B.11 Icache Flush Code The following code is loaded into memory after the system ROM image. The code is then executed to flush the SROM initialization code from the Icache. The SROM initialization code is loaded into the Icache and maps to memory beginning at address zero. 77FF0119 mt r31, flushIc C0000001 br r0, +4 .long destination 6C008000 ldl_p r0, 0x0 (r0) 47FF041F bis r31, 31, 31 47FF041F bis r31, 31, 31 . . (total of 44 bis instructions) .
C Technical Support and Ordering Information C.1 Obtaining Technical Support If you need technical support or help deciding which literature best meets your needs, call the Digital Semiconductor Information Line: United States and Canada Outside North America 1–800–332–2717 +1–508–628–4760 C.2 Ordering Digital Semiconductor Products To order the EB164, contact your local distributor.
C.
C.3 Ordering Digital Semiconductor Literature C.3 Ordering Digital Semiconductor Literature The following table lists some of the available Digital Semiconductor literature. For a complete list, contact the Digital Semiconductor Information Line.
C.4 Ordering Third-Party Literature C.4 Ordering Third-Party Literature You can order the following third-party literature directly from the vendor: Title Vendor PCI System Design Guide PCI Special Interest Group 1–800–433–5177 (U.S.) 1–503–797–4207 (International) 1–503–234–6762 (FAX) PCI Local Bus Specification, Revision 2.1 See previous entry. 82420/82430 PCIset ISA and EISA Bridges (includes 82378IB/ZB SIO) PN 290483 Intel Corporation Literature Sales P.O. Box 7641 Mt.
Glossary This glossary provides definitions for terms and acronyms associated with the EB164 and chips, specifically as applied to Alpha architecture. ASIC Application-specific integrated circuit. Bcache Backup cache. On the EB164, a board-level L3 cache with a size of between 2MB and 8MB. BIOS Basic input-output system. A set of programs encoded in read-only memory (ROM).
cache for data, and one unified 96KB L2 combined instruction and data cache. See also Bcache and write-back cache. CAS Column address strobe. CIA Control, I/O interface, and address chip. Part of the 21171 chipset. CMOS Complementary metal-oxide semiconductor. Dcache Data cache. An 8KB L1 cache reserved for data on the 21164 chip. DRAM Dynamic random-access memory. Read/write memory that must be refreshed (read from or written to) periodically to maintain the storage of information. DSW Data switch chip.
ISA Industry Standard Architecture. An 8-bit or 16-bit interface for interconnecting data storage, data processing, and peripheral control devices in a closely coupled configuration. local bus A bus that is in close proximity to the CPU and shares its speed. PCI is a local bus. PAL Programmable array logic. PCI Peripheral component interconnect. The 64-bit and 32-bit local bus developed by Intel. PGA Pin grid array. PLA Programmable logic array. PLD Programmable logic device. PLL Phase-locked loop.
RAS Row address strobe. region One of four areas in physical memory space based on the two most significant, implemented, physical address bits. RISC Reduced instruction set computing. A computing system architecture with an instruction set that is paired down and reduced in complexity so that most instructions can be performed in a single processor cycle. High-level compilers synthesize the more complex, least frequently used instructions by breaking them down into simpler instructions.
write-back cache A cache in which copies are kept of any data in the region. Read and write operations may use the copies, and write operations use additional states to determine whether there are other copies to invalidate or update. write-through cache A cache in which copies are kept of any data in the region. Read operations may use the copies, but write operations update the actual data location and either update or invalidate all copies.
Index 21171 See CIA chip or DSW chip 21171-BA See DSW chip 21171-CA See CIA chip 21171 chipset, 1–3, 3–4 See also CIA chip See also DSW chip 64-byte mode, 3–3 A Address map bridge configuration registers, A–16, A–17 operating registers, A–8, A–9 PC87312 registers, A–2 physical, A–1 SIO configuration registers, A–16, A–17 operating registers, A–8, A–9 Address space PCI configuration, A–16 dense memory, A–13 interrupt acknowledge/special cycle, A–18 sparse I/O, A–1 sparse memory, A–1 Airflow requirements, 5–
C Cache See also Bcache SIMM connectors, 2–10 Chipset overview, 3–4 Chipset support, 1–3 CIA chip, 3–4 Clock frequency multiplier, 3–16 Clock divisor jumper, 2–4 Clocks diskette, 3–18 ISA, 3–18 system, 3–16 COM1/2 connectors, 2–11 Combination controller, 3–10 Components and features, 1–1 Configuration, 2–1 to 2–14 Configuration jumpers, 2–1 Connectors, 2–8 Bcache SIMM, 2–10 debug monitor interface, 2–11 diskette, 2–11 DRAM SIMM, 2–10 fan power, 2–11, 2–14 fan sensor, 2–14 IDE drive, 2–11 ISA bus, 2–10 keybo
Functional description (cont’d) interrupts, 3–13 to 3–15 ISA bus devices, 3–8 to 3–12 main memory interface, 3–6 to 3–7 PCI devices, 3–7 to 3–8 reset and initialization, 3–19 software, 3–24 to 3–25 SROM, 3–21 system clocks, 3–16 to 3–18 J Halt button, 2–12 Hard drive connector, 2–11 Jumpers, 2–1 Bcache index, 2–5 Bcache size, 2–4 Bcache speed, 2–5 BC_RD_FAST, 2–7 boot option, 2–6 Flash ROM write-protect/write-enable, 2–7 Mini-Debugger, 2–6 system clock divisor, 2–4 system configuration, 2–1 I K I/O sp
P S Parallel port connector, 2–11 Parts ordering, C–1 PC87312 register address map, A–2 PCI bus connectors, 2–10 configuration address space, A–16 dense memory space, A–13 devices, 3–7 SIO chip, 3–8 expansion slots, 3–8 interface overview, 1–4 interrupt acknowledge/special cycle address space, A–18 sparse I/O space, A–1 sparse memory space, A–1 Peripheral component interconnect See PCI Physical board component layout, 5–2 parameters, 5–2 Ports SROM, 3–21 SROM test, 3–21 Power connectors, 2–13, 2–14 Power
System software software support, 1–5 T Technical support, C–1 Test SROM port, 3–21 Third-party documentation, C–4 Time-of-year clock, 3–11 Timing, 3–16 U Ubus, 3–8 memory device, 3–12 Utility bus See Ubus W Wave pipelining, 3–3 Index–5
