Specifications

B–4
Abbreviations, Acronyms, and Signal Mnemonics
NBUDS Upper Data Strobe. . . . . . . . . . .
NBUFCLR Buffer Clear. . . . . . . . .
NBRDBWR Read or Write. . . . . . . .
NBRKRTRP Breaker Trip. . . . . . .
NC, N/C Not Connected. . . . . . . . . . .
NCASOL Column Address Strobe Lower. . . . . . . . . .
NCASOU Column Address Strobe Upper. . . . . . . . . .
NCIACK Interrupt Acknowledge. . . . . . . . . .
NCNTCLR Dot Count Clear. . . . . . . . .
NCTC0–2 Counter/Timer Chip 0–2 Select. . . . . . . . . .
NCTRO Dot Count Read. . . . . . . . . . .
NDAV Data Available. . . . . . . . . . . .
NDMACS DMA Chip Select (68B44). . . . . . . . .
NDSTBOUT Data Strobe Out. . . . . . .
NDTEXD Data Transfer Extend. . . . . . . . . .
NEMDIS Memory Disable (Vcc ≤ 3.4V). . . . . . . . . .
NENABLE Enable Front Panel. . . . . . . . .
NEEPROM EEPROM Device Select. . . . . . . .
NEPROM0 EPROM 0 Device Select. . . . . . . . .
NEPROM1 EPROM 1 Device Select. . . . . . . . .
NEPROM2 EPROM 2 Device Select. . . . . . . . .
NFDWR Hammer Fire Data Write. . . . . . . . . . .
NFIRE Summation of Hammer Fire. . . . . . . . . . . .
NFLT Fault. . . . . . . . . . . . .
NFONT0 Font 0 Device Select. . . . . . . . . .
NFONT1 Font 1 Device Select. . . . . . . . . .
NHCK Hammer Clock. . . . . . . . . . . .
NHMC Hammer Master Clear. . . . . . . . . . . .
NHMCNF1N Hammer Load Configuration 1 Write. . . . . . .
NHMCNF3W Hammer Load Configuration 3 Write. . . . . .
NHMRBLK Hammer Data Blank. . . . . . . .
NHSCB Hammer Shift Clock Optically Isolated/Buffered. . . . . . . . . . .
NINT CTC Interrupt to CPU. . . . . . . . . . . . .
NIO0–2,5 I/O Addresses 0–2 and 5 Select. . . . . . . . . .
NIRQ Interrupt Request (Parallel). . . . . . . . . . . . .
NLD Load Hammers. . . . . . . . . . . . . .
NMC Not Master Clear (Buffered Reset). . . . . . . . . . . . .