User`s guide

Figure 5–1 details the initialization process for both single and dual-redundant
controller configurations.
Figure 5–1 Controller Initialization Flow Chart
CORE MIST
– READ/WRITE DIAGNOSTIC REGISTER
– PROGRAM CARD CONTENTS
– TIMER
– DUART
– DRAB/DRAM
– BUS PARITY
– REGISTERS
– JOURNAL SRAM
– I/D CACHE
– APPLY PATCHES
EXEC
FUNCTIONAL CODE
i960 BIST
– POLICY PROCESSOR
SELF–TEST
LOOP
CXO-3697C-MC
MIST DAEMON
– DEVICE PORTS
– HOST PORT
– CACHE MODULE
– RAID ASSIST HARDWARE
The initialization begins when the policy processor on the controller module
executes a built-in self test (BIST). If BIST fails, the controller shows no activity
and all indicators on the OCP are off. When this self-test completes, the policy
processor reads the hardware setup parameters and process control information
from the nonvolatile memory. After these parameters are located, the following
sequence executes:
1. A set of minimum integrity diagnostics (MIST) are run to verify that the bus
hardware is functional, the program card contents are valid, and that shared
memory is good.
When testing shared memory, the first 2 MB must test good; the remainder of
the memory can have up to 16 bad areas before the entire memory is declared
bad.
When MIST is complete, the program copies the controller firmware from the
program card to the first 2 MB of shared memory, using error correction code
(ECC) to correct program card errors when possible. Control is then passed
to the firmware executive. If a fault occurs at any time during core MIST, the
OCP displays an error code.
5–2 Controller Operations