User`s guide

Figure 2–1 HS Array Controller Functional Block Diagram
POLICY PROCESSOR
NVMEM
MAINTENANCE
TERMINAL
PORT
8 MB
SHARED
MEMORY
BUS
EXCHANGER
16 MB OR 32 MB
READ OR
WRITE-BACK
CACHE
(OPTION)
32KB
I/D CACHE
INTEL
80960CA/CF
µP
DIAGNOSTIC
REGISTERS
PROGRAM
CARD
DUAL
CONTROLLER
PORT
RAID ASSIST
CXO-4178D-MC
OCP
HOST
INTERFACE
DEVICE
PORT 1
DEVICE
PORT 2
DEVICE
PORT 3
DEVICE
PORT 4
DEVICE
PORT 5
DEVICE
PORT 6
2.1.1 Policy Processor Hardware
The policy processor hardware runs the controller firmware loaded from the
program card, and controls all but the low-level device and host port operations.
Shared Memory
Shared memory consists of a gate array controller and associated buffer memory.
This memory is shared between bus devices and contains data structures with
data buffers. When no cache module is present with the controller, a portion
of the controller module’s shared memory is used during normal operation as
a cache. When a read or write-back cache module is installed, the controller
module’s shared memory holds the cache module context for cache look-up
operations.
Instruction/Data Cache
Although the processor chip has an internal cache, the internal cache is not
large enough to offset performance degradation caused by shared memory. To
compensate for this, the processor chip uses a separate instruction/data (I/D)
cache. This 32-KB static RAM cache helps the processor chip achieve faster
access to instructions and variables that are in immediate use. A write-through
cache design maintains data coherency in the I/D cache.
2.1.2 Bus Exchangers
The bus exchange devices allow high-speed communication between bus devices
and shared memory. The bus exchangers allow all of the pieces of the controller
to operate together. One bus exchange device handles the address lines, while the
other one handles the data lines.
2–2 Controller Technical Description