Owner's manual

AP9050
PROTECTION INTERFACE for PMICs with
INTEGRATED OVP CONTROL
AP9050
Document number: DS35283 Rev. 1 - 2
4 of 9
www.diodes.com
March 2011
© Diodes Incorporated
NEW PRODUCT
Electrical Characteristics (V
IN
(OVP_SENSE) = 5.0V, T
J
= +25°C, unless otherwise noted)
Symbol Parameter Test Conditions Min Typ. Max Unit
Power FET
I
DSS
Zero Gate Voltage Drain Current
V
DS
= 24V, V
GS
= 0V
T
J
= 85°C
1.0
10
µA
I
GSS
Gate-to-Source Leakage Current
V
DS
= 0V, V
GS
= ±8V
80 nA
V
GS(th)
Gate Threshold Voltage
V
GS
= V
DS
, I
D
= 250µA
0.62 0.9 1.2 V
R
DS(on)
Drain-to-Source On-Resistance
(Note 7)
V
GS
= 4.5V, I
D
= 2.0A
V
GS
= 2.5V, I
D
= 2.0A
41
55
53
68
mΩ
g
FS
Forward Transconductance
V
DS
= 5V, ID = 2.0A
8 S
C
ISS
Input Capacitance
V
DS
= 15V, V
GS
= 0V,
f = 1MHz
500 pF
C
OSS
Output Capacitance
V
DS
= 15V, V
GS
= 0V,
f = 1MHz
65 pF
C
RSS
Reverse Transfer Capacitance
V
DS
= 15V, V
GS
= 0V,
f = 1MHz
50 pF
LDO (unless otherwise noted, T
J
= 25ºC, V
IN
= 5.0V)
V
OUT
Regulated Output Voltage
V
IN
= 5.5V, I
OUT
= 1mA
4.6 5.0 5.3 V
V
head
Headroom
V
IN
− V
OUT
, I
OUT
= 1.2mA,
V
IN
= 4.6V
150 mV
V
IN
− V
OUT
, I
OUT
= 10mA,
V
IN
= 4.8V, T
J
= −40 to +125°C
1000 mV
Response to Input Transient
t
pulse
Time signal is above 5.5V
V
IN
0 to 30V, < 1µs rise time,
5.0kΩ resistive load (Note 8)
5.0 µs
V
pk
Peak Voltage
V
IN
0 to 30V, < 1µs rise time,
5.0kΩ resistive load (Note 8)
9.0 V
Total Device
I
bias
Input Bias Current
V
IN
= 5.5V
110 850 µA
V
IN_min
Minimum Operating Voltage 3.0 V
Notes: 7. Pulse test width 300µs, duty cycle 2%
8. Guaranteed by design