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A3. Interrupt Test Verifies the interrupt functionality by enabling interrupt
and waiting for interrupts to occur. It waits for 500 ms
and reports an error if it cannot generate interrupts.
A4. Built-In Self-Test Runs the built-in self-test.
A5. CAM Test This test runs the content addressable memory (CAM)
read/write test. There are 48-bit patterns written to 64
entries of CAM space. The test reads back the 64 entries
and checks them against 6 patterns such as FFFF, 0000,
5555, AAAA, 55AA, AA55.
Group B: Miscellaneous Tests
B1. LED Test This test forces the link state for each link speed/duplex.
B2. EEPROM Test This test reads the serial EEPROM and verifies its integrity
by performing a cyclic redundancy check (CRC).
B3. MII Test The test writes 0s and 1s to the test bits to ensure that
the read-only bits value are not changed and that the
read/write bits are changed.
B4. Link Status Test This test reports the current link status.
Group C: Data Tests
C1. MAC Loopback Test This test transmits a 128-byte packet with the
incrementing data pattern and checks the TX and RX
flags and data integrity.
C2. PHY Loopback Test This test is the same as the MAC Loopback Test, except
that the data is routed back through a physical layer
device.
C5. PHY Loopback with CAM Enabled Test This test is the same as the PHY Loopback Test with CAM
matching enabled.
C8. MIB MAC Loopback Test This test tests each bit in the MIB counters and ensures
that the MIB counter bits are incremented when MAC
looping a packet.
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