Service manual

Page 16

port C or has been accepted from port C. Q12 provides a Frequency Update pulse for all DDS

chips. A4 and A5 are address lines for the DDS chips.

Port D has the RS-232C data lines TXD and RXD, Rotary Pulse Generator (RPG) outputs from

the two tuning dials, and additional address lines for the internal I/O ports and DDS chips.

Sheet 5 shows address decoding for the 16 data strobe lines /Strobe1 though /StrobeG. These

are used to output and input (“strobe”) data on port C to and from all boards in the rig as well as

various control functions on the Controller board. Sheets 5 and 6 show most of the internal

ports. /Strobe1 and /Strobe2 read switch data from the Front Panel board. /Strobe2 also reads

the state of the internal PTT line so that the processor knows when an external device

(microphone, etc.) has activated the Push-to-Talk. /Strobe4 (Sheet6) and /Strobe7 (Sheet 5) pro-

vide outputs that directly drive LEDs inside the pushbutton switches on the Front Panel board. /

Strobe6 (Sheet 5) and /Strobe5 (Sheet 6) provide 16 outputs that are used for a variety of con-

trol functions.

/Strobe8 through /StrobeG are fed to the Receiver, Transmitter and Tuner boards along with the

XBus to program those boards. (See Sheet 7).

Serial Bus

A serial bus is also fed to the Receiver and Transmitter boards. SCL (U13 pin 9) and SDA (U13

pin 12, as well as U12 pin 17) (Sheet 5) form a high speed I

C bus that is used to control DACs

and Digitally Controlled Potentiometers (DCPs) on the Receiver and Transmitter boards. This

bus is quiescent (not active) unless changes are needed, which helps avoid digital interference

to sensitive receiver and transmitter circuits.

DDS

Sheets 8 through 11 show the DDS chips, bandpass filters on each output, and buffer amplifiers.

Normally, DDS chips only require low pass filters on their outputs. Sienna uses bandpass filters

so as to provide a much more constant impedance across the frequencies they must output,

which helps to keep the level constant without the need for complex AGC circuitry. These de-

vices take five bytes (AD9851) or 6 bytes (AD9852) of digital data and convert it directly to a

frequency. The 0-512mV output must be converted to +/-256mV, amplified, and filtered to re-

move harmonics and other spurious signals (spurs). Close in spurs are typically down at least

70dB. A +/-1PPM TCXO provides a stable, low phase-noise 30MHz reference oscillator for all

six DDS’s.

The TV (Transmit VFO, not television!) signal coming from the TXVFO DDS (U5) on Sheet 8

is routed to a pair of Hittite GaAsFET switches which are controlled by TXVFILT (Sheet 5, pin

2 of U13). These switches allow one of two low pass filters to be applied to the output of the

TXVFO amplifier. The TXVFO covers the frequency range 12.5 to 40.4MHz, so a low pass

filter tuned for, say, 41MHz, would allow harmonics from frequencies at the lower end of the

range to pass though, so a dual range filter helps keep the output pure. The firmware performs

the switch at a TXVFO frequency of 22MHz (operating frequency of approx 11.3MHz).