Service manual

Page 22
the input offset and input bias current of the op-amp do not add a DC offset to the small AGC
voltage. U27 (pins 1,2,3) multiplies the AGC voltage by 17 in a non-inverting configuration,
resulting in a 0-1.3V output swing. The other half of U27 level shifts the 0-1.3V signal to 3.75-
5.1V which becomes the AGC voltage that is fed into U9. U10 provides the necessary negative
output that sets the differential amplifier offset. Because the LM358 is prone to a phenomenon
known as “output inversion” if the input is allowed to go below –0.3V, a Schottky protection
diode is used to keep that from happening. U10 receives its input from output “C” of a serially
programmed D/A converter (U23, sheet 8). A calibration step involves setting this voltage so
that the quiescent, no-signal AGC voltage is 3.81V.
The AGC output is level shifted back to 0.8 to 2.1V via U27 (pins 5,6,7). Since this is a loga-
rithmic signal, it is linearized by passing it through a temperature compensated antilog amplifier
consisting of U33 (pins 1,2,3), Q28 and associated parts. The output is buffered and scaled by
U33 (pins 5,6,7) and fed into a CMOS switch that selects either the S-meter signal (for all
modes except FM) and the FM relative signal strength output RSSI. The selected signal drives
the Rx meter.
An AGCOff bit is used to short out the 0-76mV AGC control voltage, forcing the AGC voltage
to stay at 3.81V and running the IF amplifier open loop at maximum gain.
For SSB mode, the AGCSlow control bit is set high, turning off Q3 and removing R77 from the
circuit. This increases the time constant to about 500ms.
The “Hang AGC” circuits on the receiver board (U10, Q22) are no longer used, and are dis-
abled by removal of jumpers JP2 and JP3.
Muting and de-sense
When operating in Full Break-in mode, in which you want to hear the receiver between dots in
CW mode, it is necessary to keep the transmitter from saturating the receiver’s amplifiers so
that recovery time is fast.
Keeping the transmitter out of the receiver’s input amplifiers requires shielding, which is ac-
complished by separating them into different compartments, and isolating them via solid state
Transmit/Receive switching. But that’s not really enough. The AGC circuitry must be forced
into maximum attenuation mode too. This is done by forcing the RFG DAC to maximum, thus
setting the AGC to 7V whenever the PTT line is active. This is done in the firmware. However,
the Sienna also has a full duplex mode, in which the Receiver is meant to be left on during
transmission. This is commonly used when operating satellites. Since external transverters are
often used for this, the transmit and receive frequencies are different, and there is less chance
for transmitter bleed-through into the receiver. Thus, if full duplex is selected, the forced 7V
AGC condition is not done.
It takes a few milliseconds for transmitter signals to make it all the way through the receiver, so
an additional signal from the controller, HRFGEn, forces the AGC to maximum during trans-
missions, and is sequenced by the Keyer processor along with the LTxEn and HRcvEn lines.