Operator's Manual
CIRCUIT DESCRIPTION
4-7
September 2001
Part No. 001-5100-001
signal for the transmit ALC IC. The synthesizer sends
a LOC signal to the transmit ALC IC. When both the
ready signal and LOC signal are available to the
transmit ALC IC, the switching transistor for the RF
power amplifier is turned on.
A coupler module samples the forward power and
the reverse power of the PA output voltage. Reverse
power is present when there is other than 50 Ω imped-
ance at the antenna port. Sampling is achieved by
coupling some of the forward and/or reverse power for
rectification and summing. The resulting DC voltage
is then applied to the transmit ALC IC as an RF
strength indicator.
The transmit ALC circuit is the core of the power
control loop. Circuits in the transmit ALC module
compare the RF strength indicator to a reference value
and generate a bias signal that is applied to the base of
a transistor. This transistor varies the DC control
voltage applied to the RF PA controlling the RF
power.
4.4 DIGITAL BOARD
4.4.1 INTRODUCTION
The Digital Signal Processing (DSP) functions
are performed by the DSP chip (U12) and the ADSIC
(U3) with the support of FLASH (U2) and SRAM
(U5, U6) memory devices. Functions previously
performed in hardware like filtering and limiting are
performed by software running in the DSP chip. The
digital board connects with the Keypad Board via J4
and with the RF board via J1.
4.4.2 DIGITAL SIGNAL PROCESSING
OVERVIEW
The DSP section consists of a DSP chip (U12),
the ADSIC (U3), two 128K x 8-bit Static RAM chips
(U5, U6), one 512K x 16-bit FLASH ROM memory
chip (U2), a UART chip (U7), a programmable logic
IC (U1), and two glue-logic chips (U4, U9). The
FLASH ROM contains the program code executed by
the DSP. Depending on the operational mode selected
for the radio, different sections of the program code in
the FLASH ROM are copied into SRAM for faster
execution.
The ADSIC is a support chip for the DSP. It
provides the interface between the DSP and the analog
signal paths, and between the DSP and the ABACUS
chip on the RF Board. Configuration of the ADSIC is
handled primarily by the microcontroller. The DSP has
access to a few memory-mapped registers on the
ADSIC.
In receive mode, the ADSIC interfaces the DSP
with the ABACUS IC on the RF Board. The ADSIC
collects the I and Q samples from the ABACUS and
performs channel filtering and frequency discrimina-
tion on the signals. The resulting demodulated signal
is routed to the DSP via the serial port for further
processing. After the DSP processing, the signal is
sent to the ADSIC Speaker D/A by writing to a
memory- mapped register. The ADSIC then converts
the processed signal from the DSP to an analog signal
and then outputs this signal to the speaker power
amplifier on the keypad board.
In transmit mode the ADSIC Microphone A/D
digitizes the analog signal from the microphone. The
DSP reads these values from a memory-mapped
register in the ADSIC. After processing, the DSP
sends the modulation signal to the ADSIC via the
serial port. In the ADSIC, the VCO D/A converts the
sampled modulation signal into an analog signal and
then routes this signal to the VCO on the RF Board.
4.4.3 RECEIVE SIGNAL PATH
The ABACUS IC on the RF Board provides a
digital back end for the receiver section. It provides a
digital output of I (in phase) and Q (quadrature)
samples which represent the IF signal at the receiver
back end. These samples are routed to the ADSIC
where the signal is filtered and frequency discrimi-
nated to recover the modulating signal.
The recovered signal is sent to the DSP chip for
processing. The ADSIC interface to the ABACUS is
comprised of four signals SBI, DIN, DIN*, and ODC.
The ODC signal is a clock the ABACUS provides to
the ADSIC. Most internal ADSIC functions are
clocked by this ODC signal at a rate of 2.4 MHz and
are available as soon as the power is supplied to the
circuitry. This signal initially may be 2.4 or 4.8 MHz
after power-up. It is programmed by the ADSIC
through the SBI signal to 2.4 MHz when the ADSIC is
REVISION 2 DIGITAL BOARD