Operator's Manual

CIRCUIT DESCRIPTION
4-9
September 2001
Part No. 001-5100-001
4.4.5 DSP CHIP (U12)
DSP chip U12 has a 16-bit data bus and a 16-bit
address bus. It has 10K words of internal SRAM from
which 0.5K are used only to store data and 9.5K are
used either for data or for program storage. The DSP
bus can access through its buses the following external
devices:
SRAM U5 and U6 - These two chips are 128K x 8
chips. U5 stores the lower byte of the word while U6
stores the higher byte. Those chips are selected by
asserting CE2 high and CE1* low. The programmable
logic IC is responsible for controlling the select lines
of these ICs.
FLASH ROM U2 - This chip is 512K x 16 words in
size. It is selected by asserting CE* low. The program-
mable logic IC is responsible for controlling the select
line of this IC.
ADSIC U3 - The ADSIC contains several registers
which can be read from or written to by the DSP. The
ADSIC IC has an output which drives a data/address
bus enable signal for the programmable logic IC.
UART U7 - This chip converts data from the DSP into
serial data. It is used to interface with the optional
encryption board.
Programmable Logic U1 - This IC arbitrates access
to the DSP’s address/data bus between the flash (U2),
SRAMs (U5,U6), and UART (U7). The DSP can
modify the memory configuration by writing to a
series of registers in the programmable logic IC. In
order to reduce power consumption, the programmable
logic IC can be “disconnected” from the DSP’s
address/data bus using the bus enable input on the
programmable logic IC (pin 44).
The DSP uses memory as data space, program
space, and I/O space as follows. Refer to Figure 4-3
for more information.
Program Space - Internal SRAM, external SRAM,
and FLASH memory.
Data Space - Internal SRAM and external SRAM.
I/O Space - Programmable logic IC, ADSIC, and the
UART.
The DSP accesses the difference spaces by setting
the corresponding lines PS*, DS*, IS* low. Only one
of these three signals can be low at a given time. When
the DSP accesses internal SRAM, none of these lines
is activated.
The programmable logic IC (PLD) acts as the
primary arbitrator of the DSP’s memory map. The
FLASH ROM and the SRAM are both mapped in the
program space and cannot both be active at the same
time. The DSP may control which type of memory is
mapped in program space by enabling the program-
mable logic IC (PLD), then manipulating a register in
the PLD. In addition, the DSP can manipulate other
registers to control paging of both the Flash and the
SRAM. Paging refers to the swapping of 64K word
blocks of Flash or SRAM into or out of the DSP’s
memory map.
FLASH ROM U2 is used to permanently store
the program to be executed in the DSP. However, it is
slow to access, so to fully utilize the speed of the DSP,
the program stored in the FLASH ROM must be
copied into the SRAM. As the size of the SRAM is
half the size of the FLASH ROM, only the code
required for the current mode of operation is copied in
the SRAM. As previously mentioned, the FLASH
ROM and the SRAM cannot be active at the same
time. Thus we use the internal data memory as a
temporary buffer to transfer the program from the
FLASH ROM to the SRAM.
The following hardware interrupts are used on the
DSP:
Connector J2 allows connection to an emulator
for debugging purposes. The emulator connects to
some dedicated pins on the DSP.
Interrupt Description
INT1* 8 kHz interrupt for speaker DAC and micro-
phone ADC from ADSIC
INT2* 125 kHz signal from ADSIC
INT3* 2 kHz timer interrupt from the Controller on
the Keypad Board.
INT4* Interrupt from the UART
NMI* Not used
DIGITAL BOARD (CONT’D)