FTXL Hardware Guide ® 078-0364-01A
Echelon, LONWORKS, LONMARK, LonTalk, Neuron, 3120, 3150, and the Echelon logo are trademarks of Echelon Corporation registered in the United States and other countries. FTXL, 3190, and ShortStack are trademarks of Echelon Corporation. Other brand and product names are trademarks or registered trademarks of their respective holders.
Welcome Echelon’s FTXL™ products enable any product that contains an Altera® Nios® II processor to quickly and inexpensively become a networked smart device. An FTXL device includes a complete ANSI/CEA 709.1-B (EN14908.1) implementation that runs on the Nios II embedded processor. Thus, the FTXL 3190™ Smart Transceiver Chip provides a simple way to add LONWORKS® networking to new or existing smart devices.
Networking Protocol, and provides a high-level introduction to LONWORKS networks and the tools and components that are used for developing, installing, operating, and maintaining them. • • LONMARK Application Layer Interoperability Guidelines. This manual describes design guidelines for developing applications for open interoperable LONWORKS devices, and is available from the LONMARK® Web site, www.lonmark.org. FT 3120 / FT 3150 Smart Transceiver Data Book (005-0139-01D).
Product Category Documentation Titles Cyclone® II and Cyclone III FPGA and device configuration Cyclone II Device Handbook Cyclone III Device Handbook Configuration Handbook USB-Blaster™ download cable USB-Blaster Download Cable User Guide Software licensing Quartus II Installation & Licensing for Windows AN 340: Altera Software Licensing Related devboards.de Product Documentation The FTXL Developer’s Kit uses the devboards.
vi
Table of Contents Welcome .........................................................................................................iii Audience ........................................................................................................iii Related Documentation ................................................................................iii Related Altera Product Documentation ................................................ iv Related devboards.de Product Documentation.......................
FPGA Design for the FTXL Transceiver ......................................................... 37 Overview ....................................................................................................... 38 Using the Reference Design ........................................................................ 38 Developing a New FPGA Design................................................................. 38 FPGA Device Requirements .................................................................
1 FTXL Hardware Overview This chapter provides an overview of the FTXL Developer’s Kit and the development process for developing a device based on the FTXL Transceiver Chip.
Overview Echelon’s Free Topology Smart Transceivers provide a well-tested and costeffective platform for many distributed control applications that are built on LONWORKS technology. For high value sensors, smart actuators, or terminal equipment controllers, an FT Smart Transceiver provides a well matched cost-tocapability ratio. For more complex applications, the Echelon FTXL Transceiver Chip provides an alternate processing platform for high-performance LONWORKS applications.
The FTXL Developer’s Kit The FTXL Developer’s Kit is a development toolkit that contains the hardware designs, software designs, and documentation needed for developing applications that use an FTXL Transceiver.
• RAM, read/write non-volatile memory (such as flash) to store configuration data, and non-volatile memory (such as flash) to store the FTXL application • The associated FPGA design and printed-circuit board (PCB) design for the device Thus, the development process for an FTXL device includes the following tasks: 1. Gather the requirements for the device 2.
• External memory (such as external RAM) for the FTXL application program • Non-volatile memory (such as flash memory) for network configuration data • Associated user I/O, such as a service pin and LED, reset button and LED, and other I/O for the device • A power supply A more robust or complex design includes additional hardware components, such as additional user I/O, support for a USB or other network interface, signal processors, or other coprocessors.
and functions with the LonTalk Compact API, so that it is possible to migrate a ShortStack™ device to use an FTXL Transceiver. An FTXL host program uses an embedded operating system (generally, a realtime operating system (RTOS)) for intra-processor communications and task management. In addition to the LonTalk API, the FTXL Developer’s Kit provides an operating system abstraction layer (OSAL) so that your host program can use any RTOS that meets your system’s requirements.
2 FTXL Developer’s Kit Hardware This chapter describes the three development boards that comprise the hardware for the FTXL Developer’s Kit.
Overview of the FTXL Developer’s Kit Hardware The FTXL Developer’s Kit requires the three hardware development boards listed in Table 2. These boards are available from devboards GmbH, www.devboards.de. You can also contact EBV Elektronik GmbH, www.ebv.com. Table 2.
Table 3. Hardware Development Platform for the Nios II Processor devboards DBC2C20 Altera Cyclone II Development Board The DBC2C20 Cyclone II Development Board includes an Altera Cyclone II EP2C20 FPGA with 20 000 logic elements (LEs) that provides flexibility and performance for a wide range of applications. The board also includes: • 16 MB SDRAM • 8 MB flash memory • 16 Mbit EPCS16 configuration device • 1 MB SRAM • Twenty-four 3.
Figure 1. Service Pin Button and LED on the DBC2C20 Development Board Table 4. FTXL Developer’s Kit Button and LED on the DBC2C20 Development Board FTXL Function DBC2C20 Function DBC2C20 Name Cyclone II Pin Assignment Service Pin Button Button 0 P25 U1 Service Pin LED LED 4 D17 U8 The FTXL Developer’s Kit does not use the two-digit seven-segment display (U24) or the navigation key (P2) on the DBC2C20 development board.
Jumper Settings The DBC2C20 development board includes three sets of jumpers (P10, P19, and P21). For the FTXL Developer’s Kit, all of these jumpers remain unmounted. Connectors and Headers The DBC2C20 development board includes 15 connectors and headers. The FTXL Developer’s Kit uses only the connectors that are shown in Figure 2 and listed in Table 5. Figure 2. Connectors and Headers on the DBC2C20 Development Board Table 5.
FTXL Function DBC2C20 Function DBC2C20 Name Main power Power supply connector P11 FTXL Transceiver Chip I/O 3.3 V I/O Connector P22 FTXL Transceiver Chip I/O 3.3 V I/O Connector P23 Figure 3 shows the connections for the P22 and P23 headers. The names in parentheses are the Cyclone II pin assignments for the I/O lines. The FTXL Developer’s Kit does not use pins 8-14 (PIO17-PIO23) on the P22 header.
The FTXL Adapter Board The primary function of the FTXL Adapter Board is to provide the 5 V power to the FTXL Transceiver Board from the 3.3 V power of the DBC2C20 development board. The FTXL Adapter Board also provides access to all of the FTXL Transceiver I/O lines through headers on the board. Connect the FTXL Adapter Board to the DBC2C20 development board by joining the FTXL Adapter Board’s J7 and J5 connectors to the DBC2C20 development board’s P22 and P23 headers.
Table 7.
J1 VDD5 VDD3.3 TXD RXD RTS CTS HRDY RST 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 J2 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 VDD5 VDD5 VDD3.3 VDD3.
LEDs The FTXL Transceiver Board includes two LEDs (D11 and D14). These LEDs are active while the FTXL Transceiver Chip is sending or receiving network data. User interaction with the FTXL Transceiver is controlled from the DBC2C20 development board. Jumper Settings The FTXL Transceiver Board includes one jumper set (J7), as described in Table 8. Table 8.
Figure 5 shows the connections for the J3 and J4 Hirose stacking headers; Figure 6 on page 18 shows the connections for their corresponding J1 and J2 receptacles. J3 VDD5 NC_A3 NC_A5 NC_A7 VDD3.
VDD3.3 VDD5 VDD3.3 VDD5 VDD3.
3 FTXL Transceiver Hardware Interface This chapter describes the hardware interface for the FTXL Transceiver Chip, which is primarily comprised of the parallel communications interface.
Overview of the Hardware Interface The hardware interface for an FTXL Transceiver is comprised of the parallel communications interface, the pin assignments and characteristics for the FTXL Transceiver Chip, and the pin assignments and characteristics for the FPGA device. This chapter describes the hardware interface. The FTXL 3190 Free Topology Smart Transceiver shares electrical and physical characteristics with the FT 3120 Smart Transceiver.
Pull-Up Resistors for Communications Lines For the parallel communications interface, you must add 10 kΩ pull-up resistors to all communication lines between the FPGA device and the FTXL Transceiver Chip (the IO0-IO10 pins of the FTXL Transceiver). These pull-up resistors prevent invalid transactions on start-up and reset of the FPGA device or the FTXL Transceiver Chip. Certain I/O pins can revert to a floating state without a pull-up resistor, which can cause unpredictable results.
FTXL Transceiver Pin Number FTXL Transceiver Pin Name Signal Name Direction Note: Signal direction is from the point of view of the FTXL Transceiver Chip. When configured in slave B mode, the Smart Transceiver defines a 3-bit control port: • IO8 is the chip select pin (CS~), and when asserted (driven low), specifies that a byte-transfer operation is in progress. This pin is driven by the FPGA device.
Figure 7. The FTXL Transceiver Parallel Interface From the point of view of the host processor, the FTXL Transceiver appears as a memory-mapped parallel I/O device with eight data bits and three control bits. The FTXL LonTalk protocol stack communicates with the FTXL Transceiver through two logical registers: an 8-bit read/write data register and a 1-bit readonly status register. The FTXL LonTalk protocol stack reads the status register’s HS bit before every read or write.
The FTXL LonTalk protocol stack and the FTXL Transceiver pass the write token alternatively between themselves on the bus in an infinite ping-pong fashion. The owner of the token has the option to write a series of data bytes, or alternatively, pass the write token without any data. The owner of the token can transfer up to 255 bytes of data. The FTXL LonTalk protocol stack reads the HS bit of the status register prior to reading or writing each data byte.
Transceiver, this pin is not part of the communications port, and does not function as a sleep control pin, but acts as in interrupt control pin. The FTXL LonTalk protocol stack uses the IRQ pin to receive an indication from the FTXL Transceiver that the network is ready, either for uplink or for downlink. The FTXL LonTalk protocol stack asserts the IRQ pin high to cause the interrupt.
• Program recovery If an application experiences unexpected behavior because of address or data corruption, a reset can recover. • VDD power down Reset ensures proper shutdown. • Memory maintenance Reset helps protect the EEPROM from major corruption. The FTXL Transceiver has four mechanisms to initiate a reset: • The RESET~ pin is asserted (pulled low) and then deasserted (returned high). • A software reset command from the parallel interface driver within the FTXL LonTalk protocol stack.
Software Controlled Reset When the CPU watchdog timer expires, or a software command to reset occurs, the RESET~ pin is asserted (pulled low) for 256 CLK1 clock cycles. The RESET~ pin external capacitor (100 ≤ CE ≤ 1000 pF) begins charging and provides the required duration of reset. Watchdog Timer The FTXL Transceiver is protected against malfunctioning software or memory faults by three watchdog timers, one for each processor that makes up the Neuron core.
When an externally generated clock is used to drive the CLK1 CMOS input pin of the FTXL Transceiver, CLK2 must be left unconnected or used to drive no more than one external CMOS load. The accuracy of the clock frequency must be ±0.02% (200 ppm) or better, to ensure that devices can correctly synchronize their bit clocks. Figure 8 shows the crystal oscillator circuit. Use the load capacitance and resistor values recommended by the manufacturer of the crystal for this circuit.
FPGA Design Pin Name FPGA Pin Number Direction Edge Capture Corresponding FTXL Transceiver Pin FTXL_RESET G16 Bidirectional Falling edge Pin 40 (RESET~) FTXL_SERVICE_LED U8 Output FTXL_AO H14 Output FTXL_CS H15 Output Pin 31 (IO8/CS~) FTXL_RW H16 Output Pin 30 (IO9/R/W~) FTXL_D0 P15 Bidirectional Pin 4 (IO0/D0/HS) FTXL_D1 J14 Bidirectional Pin 3 (IO1/D1) FTXL_D2 F14 Bidirectional Pin 2 (IO2/D2) FTXL_D3 J15 Bidirectional FTXL_D4 F15 Bidirectional FTXL_D5 H17 Bidire
and A0, and waits for the assertion of D0/HS, and then deasserts A0, asserts CS~ and reads D0-D7 to receive the data. Figure 9 shows an overview example logic analyzer trace 1 of the timing control flow when the host receives data from the FTXL Transceiver. In this example, the host receives a query status request.
Figure 10. Timing Diagram for Reading the Length Byte Figure 11 shows a detailed timing diagram for reading the data. The figure also shows the read handshake for each byte of data. However, the figure shows only the first three bytes of the data. Figure 11.
Control Flow: Host Sending Data to the FTXL Transceiver When the host program is ready to send a downlink message to the FTXL Transceiver, it asserts the A0 pin. It receives the write token after the transceiver has sent a complete message, or passed a null token. The transceiver asserts IRQ after it has received the first byte of the message (the length byte), and is ready to receive the rest of the bytes (in fast-I/O mode). It does not assert IRQ if the host sends the null token.
Write length = 0x13 Read Handshake R/W~ low -> read R/W~high -> write A0 low -> D0 is data A0 high -> D0 is handshake Handshake (D0) ready Figure 13. Timing Diagram for Writing the Length Byte Figure 14 on page 34 shows a detailed timing diagram for writing the first two bytes of the data. The figure also shows the read handshake for each byte of data.
Read Handshake (Ready) Read Handshake (Busy) Read Handshake (Ready) Write Data (0x00) Write Data (0x12) Figure 14. Timing Diagram for Writing the First Two Bytes of Data Figure 15 shows a detailed timing diagram for writing the remaining bytes of the data for the service-pin message. Write Data (0x12) Write Data (0x00) Busy Write Remaining Data: (30, 00 80 00 7f 04 d1 cd d3 01 00 9f ff ff 06 00 0a 04 11) Ready Figure 15.
Busy D=0x30 Ready D=0x04 D=0x00 D=0x80 D=0x00 D=0x7F D=0x00 D=0xD1 D=0xCD D=0xD3 D=0x01 D=0x00 D=0x9F D=0xFF D=0xFF D=0x06 D=0x0A D=0x04 D=0x11 D=0x00 Figure 16.
4 FPGA Design for the FTXL Transceiver This chapter describes FPGA design considerations for an FTXL device.
Overview The hardware for an FTXL device consists primarily of an FTXL Transceiver Chip and an Altera FPGA device. When designing your FTXL device, you can use the reference design that is included with the FTXL Developer’s Kit or you can create your own FPGA design and include the required FTXL components. Using the Reference Design The FTXL Developer’s Kit provides a reference design for the FPGA hardware design.
To develop a new FPGA design, you must use the Altera Quartus II software, version 7.2 or later (either the Web Edition or the Subscription Edition). Within the Quartus II software, you must: • Add the FTXL components to the global or project search path; see Setting Component Search Paths on page 56. • Add the FTXL components to the project; see Adding FTXL Components to an Existing Design on page 57. • Compile the project; see Building the Application Image on page 61.
multipliers, embedded memory blocks, phase-locked loops (PLLs), and high-speed differential I/O channels. See the Altera Cyclone II Device Handbook or Cyclone III Device Handbook for more information about these FPGA devices. Although the FTXL Transceiver has not been tested with an Altera Stratix®, Stratix GX, or Arria™ GX FPGA device, there is no restriction within the FTXL hardware or software design that prevents your FTXL device from using one of these types of FPGA device.
Figure 17. Quartus II Device and Pin Options Dialog See the Altera Configuration Handbook for more information about FPGA configuration devices. FTXL Components The FTXL Developer’s Kit includes components for the Altera SOPC Builder tool and the Quartus II software, as listed in Table 14. These components are installed to the [NiosEDS]\components\FTXL directory. An FTXL device must include all of these components. Table 14.
Component Name Class Name File Names Description FTXL Parallel I/O Transceiver Interface FTXL_PIO FTXL_PIO_hw.tcl Parallel I/O interface to the FTXL Transceiver FTXL Service LED FTXL_SERVICE_LED FTXL_SERVICE_LED.vhd Service LED for the FTXL device FTXL Service Pin FTXL_SERVICE_PIN FTXL Transceiver Interrupt FTXL_IRQ FTXL Transceiver Reset FTXL_RESET FTXL_SERVICE_LED_hw.tcl FTXL_SERVICE_PIN.vhd FTXL_SERVICE_PIN_hw.tcl FTXL_IRQ.vhd FTXL_IRQ_hw.tcl FTXL_RESET.vhd FTXL_RESET_hw.
• The A0 signal is delayed by two clock cycles. • The R/W~ signal is delayed by one clock cycle. Figure 19 shows the circuit detail for this component. CS_IN INPUT VCC A0_IN INPUT VCC RW_IN INPUT VCC OUTPUT A0_OUT OUTPUT CS_OUT OUTPUT RW_OUT VCC DFF D DFF PRN Q D DFF PRN Q D PRN NAND2 Q DFF D DFF DFF PRN Q D PRN Q inst7 CLRN inst18 CLK_IN INPUT VCC RESET_IN INPUT VCC inst CLRN CLRN inst2 CLRN inst5 CLRN inst6 D PRN Q CLRN inst9 sy sclk Figure 19.
Figure 20. Quartus II Component Editor Dialog for FTXL Parallel I/O Signals The data and control parts of the interface share a common Avalon tri-state bridge component. Figure 21 on page 45 shows part of the Quartus II Component Editor dialog for this component, open to the Interfaces tab, with most of the interface definitions expanded. Figure 22 on page 46 shows the same dialog, with the last interface expanded.
Figure 21.
Figure 22.
• chipselect: Select signal to enable access to the LED • write_n: Write-select signal to write to the LED • writedata: Data signal to the LED • out_port: Output signal from the LED FTXL Service Pin The FTXL service pin component defines the signals needed for an FTXL device service-pin button, including: • clk: Nios II processor clock signal • reset_n: Nios II processor reset signal • address: 2-bit address signal for the service pin button • chipselect: Select signal to enable access to the
• chipselect: Select signal to enable access to the reset pin • write_n: Write-select signal to write to the reset pin • writedata: Data signal to the reset pin • readdata: Data signal from the reset pin • bidir_port: Bidirectional signal for the reset pin Phase-Locked Loop If your FPGA design includes a phase-locked loop (PLL) component, be sure to connect one of its clock-out signals to the CLK_IN signal of the FTXL parallel I/O transceiver interface component.
• 8 MB CFI flash memory • 16 MB SDRAM These numbers correspond to the external memory provided by the DBC2C20 development board. Your FTXL device design can include as much external memory as required for your device. Addressing, Size, and IRQ Requirements For the FTXL Developer’s Kit reference design, the address assignments for the instruction master and data master components were assigned by allowing the Altera SOPC Builder tool to allocate and assign the address locations.
Component Component Name Size (Bytes) SDRAM interface for the DBC2C20 development board sdram 16 MB Table 16 lists the interrupt request (IRQ) numbers for each of the components that can generate an interrupt. Your FTXL FPGA design can specify different IRQ numbers, as long as the components retain the same relative interrupt levels. Table 16.
Within the FTXL software, the FTXL HAL is defined in two files: FtxlHal.h and FtxlHal.c. Other Hardware Design Considerations The FTXL 3190 Free Topology Smart Transceiver Chip shares electrical and physical characteristics with the FT 3120 Smart Transceiver Chip.
5 Working with the Altera Development Environments This chapter describes how to use the Altera Complete Design Suite to build the hardware design and load it into the FPGA device.
Development Tools To develop your FTXL application, you use version 7.2 or later of the Altera Complete Design Suite, as listed in Table 17. You can obtain the Altera Complete Design Suite on DVD-ROM from Altera Corporation, or you can download the Web Edition of the tools from https://www.altera.com/support/software/download/nios2/dnl-nios2.jsp. Table 17.
Using a Device Programmer for the FPGA Device To load your hardware design, software application, and the FTXL LonTalk protocol stack, into the FPGA device, you can use a device programmer, such as the Altera USB-Blaster download cable, as described in Table 18. Table 18. Device Programmer for the Nios II Processor Altera USB-Blaster Download Cable The USB-Blaster download cable interfaces to a standard PC USB port. This cable drives configuration or programming data from the PC to the device.
Setting Component Search Paths To work with an FPGA design that includes FTXL components, you must add the components to the Quartus II and SOPC Builder library paths. In addition, for the FTXL reference design, you must add the DBC2C20 components to the library paths. In the Quartus II software, you can add the FTXL components to the global library paths so that all projects can access the FTXL components, or you can add the FTXL components to the library path for a specific project.
To add FTXL components to the SOPC Builder library path: 1. Start the Quartus II software. 2. Open a Quartus II project, such as the FTXL reference design. 3. Select Tools → SOPC Builder to open the Altera SOPC Builder tool. 4. In the Altera SOPC Builder tool, select Tools → Options to open the Options dialog. 5. In the Options dialog, select IP Search Path from the Category area. 6. In the IP Search Path Options page of the Options dialog, click Add to open the Open dialog. 7.
a. Expand the Bridges and Adapters folder. b. Expand the Memory Mapped folder. c. Select Avalon-MM Tristate Bridge. d. Click Add to open the MegaWizard for the component. e. In the MegaWizard for the Avalon-MM Tristate Bridge, select Registered on the Incoming Signals page. Click Finish to add the component to the design. 6. Add the FTXL Parallel I/O Transceiver Interface component: a. Expand the FTXL folder. b. Select FTXL Parallel I/O Transceiver Interface. c.
e. If necessary, modify the assigned IRQ number for the component; see Addressing, Size, and IRQ Requirements on page 49 for recommendations about the IRQ assignments. 10. Add the FTXL Transceiver Reset component: a. Expand the FTXL folder. b. Select FTXL Transceiver Reset. c. Click Add to open the MegaWizard for the component. d. In the MegaWizard for the FTXL Transceiver Reset, there are no parameters to set. Click Finish to add the component to the design. 11.
Modifying the Quartus II Design Before you begin, ensure that the Quartus II global library or project library search path includes the FTXL components; see Setting Component Search Paths on page 56. After you generate the SOPC Builder design, you can update your Quartus II design, including updating the symbol block for the Nios II processor in the block design file (*.bdf) for the project. The updated Nios II block symbol should include the signals shown in Figure 24 and Figure 25. Figure 24.
Figure 26. Connections for FTXL_PIO_Delay Component Finally, you need to add pins to the symbol blocks for the FTXL components: 1. Right-click each component’s symbol (for example, the FTXL_PIO_Delay symbol and the Nios II processor symbol), and select Generate Pins for Symbol Ports. 2. As necessary, rename the pins. The FTXL Hardware Abstraction Layer (HAL) does not use the pin names, but instead uses the signal names, so you can assign any valid names to the pins. 3.
6. Load the modified hardware design for the Nios II processor into the FPGA device, as described in Loading the Application Image into the FPGA Device. Loading the Application Image into the FPGA Device You can choose to load the hardware and software images into the FPGA device’s RAM at the same time, or you can choose to load them separately. To load both images at the same time, or to load the images into the FTXL device’s flash memory, use the Nios IDE; see the FTXL User’s Guide for more information.
A Using the Bring-Up Application to Verify FTXL Hardware Design This chapter describes how to use the Bring-Up application that is included with the FTXL Developer’s Kit to test and verify a new or modified FTXL hardware design. The BringUp application tests the communications interface between the FTXL 3190 Free Topology Smart Transceiver and the Nios II host processor.
Overview This appendix describes the Bring-Up application that is included with the FTXL Developer’s Kit. This application implements a series of tests that exercise the hardware interface between the Nios II processor, the FTXL 3190 Free Topology Smart Transceiver, the FTXL service pin, and the FTXL service LED. You should run these tests to verify a new or modified FTXL device’s hardware design.
The FtxlHal.c file defines the following functions to handle interrupts: • LonRegisterIsr() Initializes the interrupt system, including registering the interrupt handlers described in Application Framework on page 64. • LonEnableInterrupt() Used to enable either or both of the interrupts. • LonDisableInterrupt() Used to disable either or both of the interrupts.
LonDeassertTransceiverReset() functions write to the FTXL Transceiver reset pin. Status Signals The interface includes a set of status signals that are used to determine when the FTXL Transceiver is ready to accept data or has data to be read. The status signal can be read using the FTXL HAL function LonTransceiverIsBusy(). When the LonTransceiverIsBusy() function reads the status register, the FTXL_PIO component affect FTXL Transceiver pins as listed in Table 19. Table 19.
Signal Name FTXL Transceiver Pin D2 2 D3 43 D4 42 D5 36 D6 35 D7 32 Action When LonReadTransceiverDataRegister() reads the data register, the FTXL_PIO component affects FTXL Transceiver pins as listed in Table 21. Table 21.
To write each byte, the application must first wait until LonTransceiverIsBusy() returns FALSE, and then call LonWriteTransceiverDataRegister(). After the write is complete, the FTXL Transceiver has the token, and either sends a data packet or passes the token back. The application must read the data packet or token by reading first the length byte (which indicates the number of data bytes) and then reading all data bytes. If the length byte is 0x0, there is no data.
The application uses the functions described in Interrupt Functions from the FTXL HAL on page 64 to handle interrupts. Working with the Nios IDE for the Bring-Up Application Although the Bring-Up application is designed to test the hardware design, it is a software application, and thus uses the Nios II IDE. To set up the Nios II IDE for the Bring-Up application, perform the following general steps: 1. Recommended: Create a new workspace for each example application project. 2.
Building the Application Image To build the software image for Bring-Up application: 1. Start the Nios II EDS IDE. 2. Ensure that the workspace includes the Bring-Up application project. 3. Select Project → Build Project or Project → Build All. You can also rightclick the project folder from the Nios II C/C++ Projects pane and select Build Project. The first build for a new project can take a few minutes. After you build the project, you can run it, as described in Running the Application from the Nios IDE.
The output of each test lists the test name together with an indication of whether it passed or failed. For some of the tests, additional output describes specific error conditions or wait states. Reset Test The Reset Test exercises the FTXL Transceiver’s reset line by asserting and deasserting it, and then verifying that both the status register and reset capture register behave as expected. All of the other tests in the suite require that the reset and status register behave properly.
Read Status (Busy) Host asserts reset Host deasserts reset Figure 28. Host Asserts and Deasserts Reset and Checks Status Figure 29 on page 73 shows the detail of the first read status from Figure 28. The figure shows the CS~, R/W~, A0, and HS signals just after the reset line has been asserted, and the host reads the status register. When CS~ is asserted (low), a byte transfer is in progress. R/W~ controls whether the transfer is a read or a write.
Read Handshake CS~ low -> transfer in progress RW~ high -> read A0 high -> D0 is handshake Handshake (D0) busy Figure 29. Reading Status Register during Reset Token Passing Test After the reset test runs successfully, the Token Passing Test repeatedly passes the null token between the Nios II processor and the FTXL Transceiver under program control (that is, without interrupts).
Read Handshake Write length = 0 A0 low -> D0 is data A0 high -> D0 is handshake Handshake (D0) ready Handshake (D0) busy Figure 30. Writing the Length Byte (0x00) The CS~ signal is asserted (low) every time a byte operation is in progress. The R/W~ signal is asserted (low) on a write, and deasserted (high) on a read. To read the handshake (or status) register, the A0 signal is deasserted (high), in which case D0 is the handshake signal.
The figure also shows the status being read after the token is passed. Write Read Status Length 0 (Ready) Read Status (Busy) Read Status: Write Token Read Status Ready (Busy) Figure 31. Passing the Token from the Host to the FTXL Transceiver Figure 32 on page 76 shows the state of the signals while reading a null token from the FTXL Transceiver. In this figure, the host reads the status three times. The first two times the status is busy, which indicates that the transceiver has no data to be read.
Read Null Token Read length = 0 Read Handshake Handshake (D0) busy Handshake (D0) ready A0 high -> D0 is handshake A0 low -> D0 is data Figure 32. Reading Null Token from the Transceiver Data Passing Test The Data Passing Test exercises full two-way communication between the Nios II processor and the FTXL Transceiver. As with the previous test, this test is dependent on the proper function of the reset and status registers.
Figure 33 shows the signals while writing the downlink data. Read Status (Ready) Write Length (9) Read Status Read Status Read Status (Ready) (Ready) Write 0x02, 0x04, 0x08, 0x10, (Ready) Write Data 0x20, 0x40, 0x80. Read status Write Data (0x52) between each (ready) (0x01) Read Read Read Status Status Status (Busy) (Busy) (Busy) Data bytes Figure 33.
Figure 34. Reading the Uplink Data Interrupt Test The Interrupt Test performs the same two-way communication as the Data Passing Test, but uses an interrupt service routine rather than managing the communications under program control. The test application initiates the downlink transfer by writing the length of the downlink buffer, and enables the FTXL Transceiver interrupt. The test then waits for the response to be completed.
• outputDataStream – To write a frame to the host, the frame is first copied to this buffer (including the length byte), and then the length is written to the host. The interrupt service routine writes the rest of the data. • uplinkReceived – TRUE when an uplink message has been received. • unnexpectedUplink – TRUE if the uplink message does not match the expected uplink message. • pExpectedUplinkMsg – Pointer to the expected contents of the next uplink message.
Designing Additional Tests The tests described in Running the Tests on page 70 verify the FTXL hardware design, focusing on communications between the Nios II processor and the FTXL Transceiver.
Index A A0 pin, 22 addressing requirements, 49 Altera Complete Design Suite, 54 application image building, 61 loading, 62 B bring-up application additional tests, 80 building, 70 data register, 66 framework, 64 interface, 65 interrupt, 68 interrupt functions, 64 new project, 69 Nios IDE, 69 overview, 64 reset signal, 65 running, 70 status signals, 66 tests, 70 building, application image, 61 buttons, DBC2C20 development board, 9 C clock pins, 27 communications lines, pull-ups, 21 components adding, 57 DB
N headers, 16 jumpers, 16 LEDs, 16 overview, 15 Nios II Embedded Design Suite, 54 Nios II processor, 40 H HAL, 50 handshaking, 23 hardware abstraction layer, 50 hardware interface control signal buffer, 20 data bus isolation, 20 DC-DC converter, 20 overview, 20 pull-up resistors, 21 hardware, overview, 2 headers DBC2C20 development board, 11 FTXL Adapter Board, 13 FTXL Transceiver Board, 16 host receive, control flow, 29 host send, control flow, 32 HS pin, 22 I I/O pins, 24 interface.
signals.
www.echelon.
