I/O Model Reference for Smart Transceivers and Neuron Chips ® 0 7 8 - 0 3 9 2 - 0 1B
Echelon, LONWORKS, LONMARK, NodeBuilder, LonTalk, Neuron, 3120, 3150, ShortStack, LonMaker, and the Echelon logo are trademarks of Echelon Corporation registered in the United States and other countries. FTXL, 3170, and 3190 are trademarks of the Echelon Corporation. Other brand and product names are trademarks or registered trademarks of their respective holders.
Welcome For the various input/ouput (I/O) pins on an Echelon® Smart Transceiver, an Echelon Neuron® 5000 Processor, or Series 3100 Neuron Chip, Echelon’s Neuron C programming language provides a set of I/O models that allow a program to define I/O objects. An I/O model is an abstract definition (including the relevant firmware driver) of hardware I/O for a Neuron Chip or Smart Transceiver; an I/O object is software instance of the specific I/O model.
• Mini FX User’s Guide (078-0398-01A). This manual describes how to use the Mini FX Evaluation Kit. You can use the Mini FX Evaluation Kit to develop a prototype or production control system that requires networking, or to evaluate the development of applications for such control networks using the LONWORKS platform. • Neuron C Programmer’s Guide (078-0002-01H). This manual describes • Neuron C Reference Guide (078-0140-01F).
Table of Contents Welcome .........................................................................................................iii Audience ........................................................................................................iii Related Documentation ................................................................................iii Chapter 1. Introduction ..................................................................................... 1 Overview .................................
Nibble Output Example.................................................................. 43 Touch Input/Output ..................................................................................... 43 Hardware Considerations ..................................................................... 44 Programming Considerations ............................................................... 46 Syntax .............................................................................................. 46 Usage ...........
Example ........................................................................................... 88 Magtrack1 Input .......................................................................................... 89 Hardware Considerations ..................................................................... 89 Programming Considerations ............................................................... 90 Syntax ..............................................................................................
Syntax ............................................................................................ 132 Usage ............................................................................................. 133 Example ......................................................................................... 133 Infrared Input ............................................................................................ 134 Hardware Considerations ..................................................................
Hardware Considerations ................................................................... 162 Programming Considerations ............................................................. 163 Syntax ............................................................................................ 164 Usage ............................................................................................. 165 Example .........................................................................................
Index................................................................................................................
1 Introduction This chapter provides an overview of the available I/O models for Series 3100 devices and Series 5000 devices. It includes considerations for hardware, programming, and timing.
Overview Echelon’s Neuron Chips and Smart Transceivers connect to application-specific external hardware through 11 or 12 I/O pins, named IO0-IO11. You can configure these pins to provide flexible input and output (I/O) functions with minimal external circuitry. These functions are described as I/O models. The Neuron C programming language allows the application programmer to declare I/O objects that use one or more I/O pins.
• Timer/Counter I/O Models use a timer/counter circuit in the Neuron Chip or Smart Transceiver. Each Neuron Chip and each Smart Transceiver has two timer/counter circuits: One whose input can be multiplexed, and one with a dedicated input.
Table 1.
Table 3.
Table 4. Summary of the Timer/Counter Input Models I/O Model Applicable I/O Pins Dualslope Input IO0, IO1 + (one of IO4 – IO7) Edgelog Input Total Pins per Object Input/Output Value Page 2 Comparator output of the dualslope converter logic 125 IO4 1 A stream of input transitions 129 Infrared Input IO4 – IO7 1 Encoded data stream from an infrared demodulator 134 Ontime Input IO4 – IO7 1 Pulse width of 0.2 μs – 1.678 s 138 Period Input IO4 – IO7 1 Signal period of 0.2 μs – 1.
I/O Model Applicable I/O Pins Total Pins per Object Pulsewidth Output IO0, IO1 Stretched Triac Output1 Input/Output Value Page 1 0 – 100% duty cycle pulse train 171 IO0, IO1 + (one of IO4 – IO7) 2 Delay of output pulse with respect to input edge 174 Triac Output2 IO0, IO1 + (one of IO4 – IO7) 2 Delay of output pulse with respect to input edge 179 TriggeredCount Output IO0, IO1 + (one of IO4 – IO7) 2 Output pulse controlled by counting input edges 183 Notes: 1.
The following guidelines for declaring I/O object types apply to the I/O models shown in Figure 1 on page 9: 8 • Up to 16 I/O objects can be declared. • Timer/counter 1 can be multiplexed for up to four input objects. • The neurowire, i2c, magcard, magcard_bitstream, magtrack1, and serial I/O models are mutually exclusive. One or more of a single type of these I/O models can be declared in one program.
I/O Pin 0 1 2 3 4 5 Byte Input, Byte Output All Pins 0 – 7 Leveldetect Input Any Pin 0 – 7 DIRECT I/O MODELS 6 7 8 9 10 11 Any Pin Bit Input, Bit Output Any Four Adjacent Pins Nibble Input, Nibble Output Touch I/O PARALLEL I/O MODELS SERIAL I/O MODELS Muxbus I/O Data Pins 0 – 7 ALS WS Master/Slave A Data Pins 0 – 7 CS R/W HS Slave B Data Pins 0 – 7 CS R/W A0 RS Parallel I/O Bitshift Input, Bitshift Output C D I2C I/O C D C D C D C D C D C D IRQ C Magcard Bi
Example: The following I/O models can be combined for a Neuron Chip or Smart Transceiver: • 1 parallel I/O model (on IO_0..IO10) OR • 1 muxbus I/O model (on IO_0..IO10) OR • A combination of any or all of the other I/O models A through E shown in Table 6: Table 6.
used by the application are tied high or low on the PC board, or are left unconnected and configured as a bit output by the application in order to prevent unnecessary power consumption. See the PL 3120 / PL 3150 / PL 3170 Power Line Smart Transceiver Data Book for more information. For Series 5000 devices, the I/O pins do not have configurable pull-ups or high current-sink capability. If your I/O circuitry requires pull-up resistors, you must add them to the hardware design for the device.
For Series 5000 devices, the sample rate is equivalent to the system clock rate. For a signal to be reliably synchronized with an 80 MHz system clock, it must be at least 17.5 ns in duration; see Figure 4. t setup 5 ns thold 0 ns IO0-IO11 Inputs (17.5 ns pulse) 80 MHz System Clock Figure 4. Synchronization of External Signals for Series 5000 Devices Any event that lasts longer than 220 ns (for a Series 3100 device at 10 MHz) or 17.
page 107 for more information. Also, for Series 5000 devices, when hardware interrupt tasks run in the application (APP) processor (for the two lowest clock rates), the contribution of interrupt processing, including the application-specific interrupt tasks, directly adds to the scheduler delay. However, at higher clock rates, the contribution of interrupts is very small and approximately constant.
IO_out call IO_out call t ww IO_out call t ww t sol IO_0 TIME 1st when clause end-of-loop processing begins 2nd when clause 1st when clause (Not to scale) Figure 5.
The total latency for a particular function call, from start to end, has two separate parts: • Processing time required before the actual hardware I/O update (read or write) occurs • The time required to finish the current function call and return to the application program Overall accuracy is always related to the accuracy of the clock in (CLK1 or XIN) input of the Neuron Chip or Smart Transceiver. Timing diagrams are provided for all non-trivial cases to clarify the parameters given.
• • • • Driving a Seven Segment Display with the Neuron Chip engineering bulletin (part no. 005-0014-01) Neuron Chip Quadrature Input Function Interface engineering bulletin (part no. 005-0003-01) Parallel I/O Interface to the Neuron Chip engineering bulletin (part no. 005-0021-01) EIA-232C Serial Interfacing with the Neuron Chip engineering bulletin (part no.
io-object-name A user-supplied name for the I/O object, in the ANSI C format for variable identifiers. The description for each I/O object includes a detailed explanation of the syntax for each I/O model. Example: A logic level needs to be measured at the IO3 input pin of the device, which is named IO_3 in Neuron C. The pin is connected to a proximity detector, as its programmatic name indicates.
The IO2 pin is an output bit I/O object (because the output is declared last). Assuming that the io_set_direction( ) function is not called, a subsequent call to the io_out( ) function for ioPoint2 sets the level of this pin. A call to the io_in( ) function for ioPoint1 can then be used to read back the actual pin level of this output object. Multiplexing I/O Models Input to one of the timer/counter circuits can be multiplexed among pins IO_4 to IO_7 or provide output to IO_0.
functions because they are included by the Neuron C compiler. The compiler enforces type checking for the parameters of these functions. Table 7.
return-value = io_in ( io-object-name [, args] ) return-value The current value read from the input device. The data type of the return value and its semantics are a function of the I/O model implemented by this I/O object. io-object-name The name for the I/O object, which corresponds to the io-object-name in the I/O object declaration. args Arguments that depend on the type of the I/O model. Some of these arguments can also appear in the I/O object declaration.
#define ON 1 #define OFF 0 IO_0 output bit ioRelay; // or IO_0 output bit ioRelay = ON; The second (commented out) declaration in the example above uses an initializer, which tells the system that following a reset, the ioRelay object output value should initially be set to 1. The default initial value is 0. Now you can control the state of ioRelay by using the io_out( ) function: if (flowTotal > 500) { io_out(ioRelay, ON); } The io_out() function takes a valid C expression for its argument.
} } ... I/O Events An alternative to using the explicit io_in( ) function is to associate an input object with a predefined event or interrupt. The two I/O-related predefined events are: • io_changes • io_update_occurs These events are used only with input objects. When they are evaluated, both the io_update_occurs and io_changes events perform an implicit io_in( ) function call to obtain an input value for the object. Your program can access this input value by using the input_value variable.
I/O Model Event ontime Event occurs if the measured time has changed from the last time. period Event occurs if the measured time has changed from the last time. pulsecount Event occurs if the number of counts measured has changed from the last count. quadrature Event occurs if the number of counts measured has changed from the last count. Example: A program could use the io_changes event to detect changes in an ioProximity input object: when (io_changes(ioProximity)) { . . .
input_value Variable You use the input_value variable to retrieve the input value for an I/O object when either the io_update_occurs event or the io_changes event occurs. The input_value built-in variable is a signed long, and it can be cast in the same manner as any other C variable. Example: when (io_update_occurs(ioDevice)) { if (input_value > 2) { . . .
Using Functions or Events To determine whether an input value is new, you can use the io_in( ) function with the input_is_new variable or you can use the io_update_occurs event with the input_value variable. Which method you choose depends on the specific I/O model and the specific task that the program is designed to perform. The I/O event mechanism tends to be the simpler method, where the Neuron scheduler decides when to perform the I/O functions.
I/O Functions for Timer/Counter Objects For multiplexed I/O objects, the last timer/counter I/O object declared in the program is the first to take effect after a reset. To change the selected I/O object, use the io_select( ) function to specify which of the multiplexed pins is the owner of the timer/counter circuit.
} when (io_update_occurs(inOntime)) { io_select(inPeriod, 3); } When a new clock is set for an I/O object using the io_select( ) function, this clock remains in effect until a new value is explicitly set. The next io_select( ) call for the same I/O object resets the clock to the value specified in the I/O object declaration if there is no clock argument in the io_select( ) call.
int slope1Clock = 2; IO_5 input ontime clock (2) ioSlope1; IO_6 input period clock (1) ioCycleA; // Following reset, the ioCycleA object is selected // because it is the last object declared using the mux when (io_update_occurs(ioSlope1)) { if (input_value > 0x4000 && slope1Clock == 2) { // Range down (slower) slope1Clock = 4; io_set_clock(ioSlope1, slope1Clock); } else if (input_value < 0x4000 && slope1Clock == 4) { // Range up (faster) slope1Clock = 2; io_set_clock(ioSlope1, slope1Clock); } else { // Save
returned by subsequent calls to io_in( ) until a new value is latched based on the timing in the hardware. The period input and ontime input models latch a new value on the falling edge of the input signal (or if the invert keyword is used, these models latch the new value on the rising edge of the input signal). The pulsecount input model latches a new value every 0.8388608 seconds. See the Neuron C Programmer’s Guide for more information about timer frequencies and timer accuracy.
2 Direct I/O Models This chapter describes direct input/output models. Direct I/O models are based on a logic level at the I/O pins; none of the Neuron Chip or Smart Transceiver hardware’s timer/counters are used in conjunction with these I/O objects. These models can be used in multiple, overlapping combinations within the same Neuron Chip or Smart Transceiver.
Bit Input/Output The bit I/O model is used to read or control the logical state of a single pin, where 0 represents low and 1 represents high. This model applies to Series 3100 Neuron Chips and Smart Transceivers, and to Series 5000 Neuron Processors and Smart Transceivers. Hardware Considerations Pins IO0 – IO11 can be individually configured as single-bit input or output ports.
t fin t ret INPUT TIME INPUT PIN SAMPLED START OF io_in() END OF io_in() Figure 8. Bit Input Timing Table 11. Bit Input Latency Values for Series 3100 Devices Symbol Description Typical at 10 MHz tfin Function call to sample IO0 – IO10 IO11 41 μs 8.4 μs tret Return from function IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7 IO8 IO9 IO10 IO11 19 μs 23.4 μs 27.9 μs 32.3 μs 36.7 μs 41.2 μs 45.6 μs 50 μs 19 μs 23.4 μs 27.9 μs 7.
Table 12. Bit Output Latency Values for Series 3100 Devices Symbol Description Typical at 10 MHz tfout Function call to update IO3 – IO5, IO11 All others 69 μs 60 μs tret Return from function IO0 – IO11 5 μs Programming Considerations For bit input, the data type of the return value for io_in( ) is an unsigned short. For bit output, the output value is treated as a Boolean value, so any non-zero value is treated as a 1. The bit input and output models are both direct I/O models.
Usage unsigned int input-value; unsigned int output-value; input-value = io_in(io-object-name); io_out(io-object-name, output-value); Bit Input Example IO_1 input bit ioSwitch; // declares pin IO1 as a // bit input object named ioSwitch unsigned int switch_on_off; ... when (reset) { io_change_init(ioSwitch); } when (io_changes(ioSwitch)) { switch_on_off = input_value; } Bit Output Example IO_2 output bit ioLed; unsigned int led_on_off; ... when(...
IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7 IO8 IO9 IO10 IO11 IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7 IO8 IO9 IO10 IO11 High Current Sink Drivers Optional Pull-Up Resistors Figure 10. Byte I/O for Series 3100 Devices Figure 11 and Figure 12 show the byte input and byte output latency times, respectively. These are the times from the call to the io_in() or io_out() function, until a value is returned. The direction of bit ports can be changed between input and output dynamically by using the io_set_direction() function.
Table 14. Byte Output Latency Values for Series 3100 Devices Symbol Description Typical at 10 MHz tfout Function call to update 57 μs tret Return from function 5 μs Programming Considerations For byte input/output, the data type of the return value for io_in( ), and the data type of the output value for io_out( ), is an unsigned short. Syntax IO_0 input byte io-object-name; IO_0 output byte io-object-name [=initial-output-level]; IO_0 Specifies pin IO_0 as the least significant bit of the byte.
} when (io_changes(ioKeyboard)) { character = input_value; } Byte Output Example IO_0 output byte ioDisplay; ... when (...) { io_out(ioDisplay, '?'); } Leveldetect Input The leveldetect I/O model is used to detect a low level (logical zero) on a single pin, for example, for a proximity detector. This model applies to Series 3100 Neuron Chips and Smart Transceivers, and to Series 5000 Neuron Processors and Smart Transceivers.
Figure 13. Leveldetect for Series 3100 Devices and Input Timing Table 15. Leveldetect Input Latency Values for Series 3100 Devices Symbol Description Typical at 10 MHz tfin Function call to sample IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7 35 μs 39.4 μs 43.9 μs 48.3 μs 52.7 μs 57.2 μs 61.6 μs 66 μs Return from function 32 μs tret Programming Considerations The state of the input is latched in hardware every 50 ns for a Series 3100 device with a 40 MHz input clock or every 12.
independently from I/O objects, and can be triggered by positive or negative level, rising or falling edge, or either edge of the I/O signal (regardless of the I/O object’s direction), I/O interrupts can often be used in place of a leveldetect object. For Series 3100 devices, add a #pragma enable_io_pullups directive to enable the Neuron Chip's or Smart Transceiver's built-in pull-up resistors on pins IO_4 through IO_7. Syntax pin [input] leveldetect io-object-name; pin An I/O pin.
The direction of nibble ports can be changed between input and output dynamically under application control (see Programming Considerations on page 42). The least-significant bit (LSB) of the input data is determined by the object declaration and can be any of the IO0 – IO4 pins. For Series 3100 devices, the high (20 mA) current sink capability of pins IO0 – IO3 (see Figure 14) allows these pins to drive many I/O devices directly. Figure 14.
Figure 16. Nibble Output Timing Table 17. Nibble Output Latency Values for Series 3100 Devices Symbol Description Typical at 10 MHz tfout Function call to update IO0 IO1 IO2 IO3 IO4 78 μs 89.8 μs 101.5 μs 113.5 μs 125 μs tret Return from function IO0 – IO4 5 μs Programming Considerations For nibble input/output, the data type of return_value for the io_in( ) function, and the data type of the output value for the io_out( ) function is an unsigned short.
through IO_4. The lowest numbered I/O pin is defined as the least significant bit of the nibble data. io-object-name A user-specified name for the I/O object, in the ANSI C format for variable identifiers. initial-output-level A constant expression, in ANSI C format for initializers, used to set the state of the output pin of the I/O object at initialization. The initial state can be from 0 to 15. The default is 0.
designated I/O pin. This I/O pin is operated as an open-drain device in order to support the interface. Up to 255 bytes of data can be transferred at a time. For more information about this protocol, and the devices that it supports, see application note 937, Book of iButton Standards, from Maxim Integrated Products. This model applies to Series 3100 Neuron Chips and Smart Transceivers, and to Series 5000 Neuron Processors and Smart Transceivers.
Figure 17. Touch I/O for Series 3100 Devices and Timing Table 18. Touch I/O Latency Values for Series 3100 Devices Symbol Description Minimum Typical Maximum trsto Reset call to data line low — 60.0 μs — trstl Reset pulse width — 500 μs — tpdh Reset pulse release to data line high 10 MHz 5 MHz 4.8 μs 9.6 μs tpdl Presence pulse width — 120.0 μs — twh Data line high detect to presence pulse — 80 μs — trret Return from reset function — 12.
Symbol Description Minimum twrd Start pulse edge to Smart Transceiver releasing the data line 10 MHz 5 MHz — Inter-bit delay 10 MHz 5 MHz — Return from I/O call — tibd tret Typical Maximum — 66.6 μs 72.0 μs — 61.2 μs 122.4 μs 42.6 μs — The leveldetect input model can be used for detection of asynchronous attachments of 1-Wire devices to the Smart Transceiver. In such a case, the leveldetect input object is overlaid on top of the Touch I/O object.
This argument has a minimum value of 7.2 μs (t_low = 1) from the start of tLOW. The incremental resolution of t_low is 3 μs, so the control range is 4.2 + n * 3 (in μs) where n is 1 to 255, and a t-low value of 0 is equivalent to n=256. • • t-rdi The length of tRDI. This is the interval where the Neuron firmware asserts either a low or a high on the 1-Wire bus, depending on the output data bit polarity. For read operations, this data polarity is always high. This argument has a minimum value of 7.
limited to 275 μs, after which the touch_reset( ) function returns a -1 value with the assumption that the 1-Wire bus is stuck low. There also is a minimum value for this period: for a Series 3100 device, it must be >4.8 μs @10 MHz, or >9.6 μs @5 MHz; for a Series 5000 device, it must be >0.3 μs @ 80 MHz, or >4.8 μs @5 MHz. After the 1-Wire bus has appeared to go high, the Neuron firmware waits for the presence pulse for a period up to 80 μs.
the 1-Wire bus. The last_discrepancy variable is used internally and should not be modified. To start a new search: 1. Call touch_first( ) 2. As long as the search_done flag is not set, call touch_next( ) as many times as are required. For a Series 3100 device, each call to touch_first( ) or touch_next( ) takes 41 ms to execute at 10 MHz (63 ms at 5 MHz) when a device is being read.
Example // In this example, a leveldetect input is used on the // 1-Wire interface to detect the 'presence' signal // when a Touch Memory device appears on the bus. #include #define DS_READ_ROM 0x33 unsigned int data[8]; IO_3 input leveldetect ioPresence; IO_3 touch ioTouchWire; . . . when (io_in(ioPresence) == 1) { unsigned int i, crc; // Reset the device using touch_reset(). // Skip if there is no device sensed.
3 Parallel I/O Models This chapter describes parallel input/output models. Parallel I/O models are used for high-speed bidirectional I/O.
Muxbus Input/Output The multiplexed bus (muxbus) I/O model provides a means of performing parallel I/O data transfers between a Smart Transceiver and an attached peripheral device or processor. This I/O model allows you to interface with any device that requires an address and a data bus, such as a programmable universal asynchronous receiver/transmitter (UART). The muxbus I/O model uses eleven I/O pins to form an 8-bit address and bidirectional data bus interface.
Figure 18. Muxbus I/O for Series 3100 Devices and Timing Table 20. Muxbus I/O Latency Values for Series 3100 Devices Symbol Description Minimum Typical Maximum tfout io_out() call to valid address — 26.4 μs — tas Address valid to address strobe — 10.8 μs — tahw Address hold for write — 4.8 μs — tahr Address hold for read — 6.6 μs — twas Address strobe width — 6.6 μs — twrs Read strobe width — 10.8 μs — twws Write strobe width — 10.
Symbol Description Minimum Typical Maximum tfin io_in() call to valid address — 26.4 μs — trret Function return from read — 4.2 μs — twret Function return from write — 4.2 μs — Programming Considerations For a muxbus output object, the io_out( ) function requires an optional 8-bit address argument, and an 8-bit data argument.
A user-specified name for the I/O object, in the ANSI C format for variable identifiers. Usage unsigned int data-byte; data-byte = io_in(io-object-name, address); data-byte = io_in(io-object-name); io_out(io-object-name, address, data-byte); io_out(io-object-name, data-byte); Example IO_0 muxbus ioMuxBus; when (. . .) { // Write two bytes to addresses 0x20 and 0x21, // and wait for the data at 0x20 to contain // the 0x80 value.
• Master and slave A connections are typically used for parallel port interfaces and for Neuron Chip/Smart Transceiver to Neuron Chip/Smart Transceiver communication. • Slave B connections are typically used for communicating from a microprocessor bus to a Neuron Chip or Smart Transceiver. This model applies to Series 3100 Neuron Chips and Smart Transceivers, and to Series 5000 Neuron Processors and Smart Transceivers.
Figure 19. Master Mode and Slave A Mode The maximum data transfer rate is 1 byte per 4 processor instruction cycles (2.4 μs per byte for a Series 3100 device with a 10 MHz input clock rate, or 300 ns per byte for a Series 5000 device with an 80 MHz system clock). The data transfer rate scales proportionally to the input clock rate (a master write is a slave read).
Table 21.
Symbol Description Minimum Typical Maximum Notes: 1. XIN represents the period of the Smart Transceiver input clock (100 ns for a Series 3100 device at 10 MHz), or the period of the system clock for a Series 5000 device (12.5 ns at 80 MHz). 2. Refer to the appropriate Neuron Chip or Smart Transceiver data sheet for detailed measurement information. 3.
Table 22.
input buffer of the slave (because the master owns the token after reset and has the first option to write on the bus) and the slave then outputs data to the input buffer of the master. You can view the buffers using the NodeBuilder debugger to verify that the transfer was completed. The master transmits the pattern [5,1,1,1,1,1] to the slave and the slave transmits the pattern [7,1,2,3,4,5,6,7,0,0,0,0,0,0] to the master.
unsigned int i; when (reset) { outData.length = OUT_LEN; // assign output length for(i=0; i
unsigned int buffer[MAX_IN]; } inData; unsigned int i; when (reset) { outData.length = OUT_LEN; // assign output length for(i=0; i
READ ONLY STATUS REGISTER READ/WRITE DATA REGISTER HS D0 X SLAVE B D0/HS D1 IO3 D4 IO4 D2 X D3 D5 X D4 D6 HS/D0 – D7 IO2 D3 X IO5 IO6 D7 X D5 X D6 X D7 R/W~ = 1 IO10 = 1 IO1 D2 D1 R/W~ = 1 OR R/W~ = 0 OR 1 IO10 = 0 IO10 = 1 IO0 IO7 CS~ IO8 R/W~ IO9 A0 IO10 IRQ IO11 Figure 22. Parallel I/O Master/Slave B as a Memory-Mapped Device Figure 23. Slave B Mode Timing Table 23.
Symbol Description Minimum Typical Maximum tsbas A0 setup to falling edge of CS~ 10 ns — — tsbah A0 hold after rising edge of CS~ 0 ns — — tsbwdv CS~ to write data valid — — 50 ns tsbwdh Write data hold after rising edge of CS~ (Notes 2, 3) 0 ns 30 ns — tsbwdz CS~ rising edge to Slave B release data bus (Note 2) — — 50 ns tsbrds Read data setup before rising edge of CS~ 25 ns — — tsbrdh Read data setup before rising edge of CS~ 10 ns — — Notes: 1.
Token Passing Virtual token passing is implemented to eliminate the possibility of data bus contention. The token is owned by the master after synchronization and is passed between the master and slave devices. After each data transfer is completed, the token owner writes an end of message (EOM) (0x00) to indicate that the transfer is complete. The EOM is never read. Instead, “processing the EOM” indicates passing of the token.
Neuron Chip Or Smart Transceiver Master Has Token MASTER Write Data Pass Token CMP_RESYNC Write Data Pass Token CMP_ACK RESYNC Slave Has Token SLAVE Figure 24. Handshake Protocol Sequence between Master and Slave When in possession of the write token, the device (Neuron Chip, Smart Transceiver, or a host processor) can transfer up to 255 bytes of data. The stream of data bytes is preceded by the command and length bytes.
Step Master Slave 3 4 Read RESYNC Write EOM End of message (EOM=0x00) 5 Process EOM 6 Write ACKSYNC 7 Comment Slave acknowledges resynching (0x07) Read ACKSYNC 8 Write EOM 9 Process EOM 10 (Owns Token) Master owns token when reset Table 25.
Table 26.
Table 28. Slave Passes Token to Master Step Master Slave 1 (Owns Token) 2 Write NULL 3 Read NULL 4 Process EOM 6 (Owns Token) Slave has no data to send to master NULL=0x00 Write EOM 5 Comment End of data transfer (EOM=0x00) Exchange token Using the IRQ Signal A Series 5000 device can use the IRQ pin as an indication that the network is ready, either for uplink or for downlink.
Neuron C Resources In order to use the parallel I/O model of the Neuron Chip or Smart Transceiver, the io_in( ) and io_out( ) functions require a pointer to the parallel_io_interface structure: struct parallel_io_interface { unsigned length; // length of data field unsigned data[MAXLENGTH]; // data field } piofc; The parallel_io_interface structure must be declared in the application program, with an appropriate definition of MAXLENGTH to signify the largest expected buffer size for any data transfer, up to
Syntax IO_0 parallel slave | slave_b | master io-object-name; IO_0 Parallel input/output requires eleven pins and must specify pin IO_0. Table 29 shows how the pins are used. Table 29.
Example The following example shows how to use the io_in_ready and io_out_ready events, in conjunction with the io_out_request( ) function, to handle parallel I/O processing. #define DATA_SIZE 255 struct parallel_io_interface { unsigned int length; unsigned int data [DATA_SIZE]; } piofc; IO_0 parallel slave slaveBus; // length of data field // data field // ready to input data when (io_in_ready(slaveBus)) { piofc.
4 Serial I/O Models This chapter describes serial input/output models. Serial I/O objects are used for transferring data serially over a pin or a set of pins. Only one type of serial I/O model can be used within a single Neuron Chip or Smart Transceiver. Both the input and output versions of the serial type can coexist within a single Neuron Chip or Smart Transceiver.
Bitshift Input/Output The bitshift I/O model is used to shift a data word of up to 16 bits into or out of the Neuron Chip or Smart Transceiver. Data is clocked in and out by an internally generated clock. This model is useful for transferring data to external logic that uses shift registers. This model applies to Series 3100 Neuron Chips and Smart Transceivers, and to Series 5000 Neuron Processors and Smart Transceivers.
INPUT SAMPLED t hold t fin t aet t tae OUTPUT CLOCK t ret DATA IN START OF io_in() END OF io_in() Active clock edge assumed to be positive in the above diagram. Figure 26. Bitshift Input Timing Table 30. Bitshift Input Latency Values for Series 3100 Devices Symbol Description Typical at 10 MHz tfin Function call to first edge 156.6 μs tret Return from function 5.4 μs thold Active clock edge to sampling of input data 15 kbps bit rate 10 kbps bit rate 1 kbps bit rate 9 μs 40.8 μs 938.
tsetup tfin taet ttae OUTPUT CLOCK tret DATA OUT START OF io_in() END OF io_in() Active clock edge assumed to be positive in the above diagram. Figure 27. Bitshift Output Timing Table 31. Bitshift Output Latency Values for Series 3100 Devices Symbol Description Typical at 10 MHz tfin Function call to first data out stable 16-bit shift count 1-bit shift count 185.3 μs 337.6 μs tret Return from function 10.
Programming Considerations For bitshift input/output, the data type of the return value for io_in( ), and the data type of the output value for io_out( ), is an unsigned long. When using multiple serial I/O devices that have differing bit rates, you must use the following compiler directive: #pragma enable_multiple_baud. This pragma must appear prior to the use of any I/O function (such as io_in( ) or io_out( )). Figure 28.
kbaud (const-expr) Specifies the bit rate. The expression const-expr can be 1, 10, or 15. The default is 15. The firmware uses this value as a multiplier based on the Series 3100 input clock or Series 5000 system clock. For example, for a Series 3100 device at 10 MHz, kbaud(15) yields 15 kbps; for a Series 5000 device at 10 MHz, kbaud(15) yields 30 kbps. The bit rate scales proportionally with the input or system clock.
Hardware Considerations The Smart Transceiver is always the master, with IO8 as the serial clock (SCL) signal and IO9 the serial data (SDA) signal. Alternatively, IO0 can be used as the serial clock (SCL) and IO1 as the serial data (SDA). These I/O lines are operated in the open-drain mode in order to accommodate the special requirements of the I2C protocol. With the exception of two pull-up resistors, no additional external components are necessary for interfacing a Smart Transceiver to an I2C device.
Symbol Description Minimum Typical Maximum tstart End of start condition io_in() io_out() 5.4 μs 5.4 μs — — tcla End of start to start of address io_in() io_out() 24.0 μs 24.0 μs — — tcld SCL low to data for io_out() 24.6 μs — — tdch Data to SCL high for io_out() 7.2 μs — — tchcl Clock high to clock low for io_out() 12.6 μs — — tchd SCL high to data sampling for io_in() 13.2 μs — — tdcl Data sample to SCL low for io_in() 7.
For I2C input/output, io_in( ) and io_out( ) return a 0 or 1 value reflecting the fail (0) or pass (1) status of the transfer. A failed status indicates that the addressed device did not acknowledge positively on the bus, or that the SCL was low at the start of the transfer. For more information on this protocol and the devices that it supports, see documentation for Philips Semiconductors Microcontroller Products, under I2C bus descriptions.
// i2c I/O object with the stop condition specified return-value = io_in(io-object-name, data-buffer, dev-address, count, stop); return-value = io_out(io-object-name, data-buffer, dev-address, count, stop); Example #define AD_ADDR 0x48 // address of the A/D converter IO_8 i2c ioI2C; unsigned int buffer[5]; unsigned int control; boolean result; . . . when (...) { // Read the A/D converter. // First, write a control word byte.
Programming Considerations The data item unit is a single bit, and the maxbits and count values indicate the number of bits that can be read, or have been read, respectively. In case of a timeout, the count will be less than maxbits. Syntax IO_8 [input] magcard_bitstream [timeout (pin-nbr)] [clockedge (+|-)] [invert] io-object-name; IO_8 Specifies pin IO_8. The magcard bitstream input requires both pins IO_8 and IO_9. Pin IO_8 is the negative-going clock, IO_9 is the serial data input.
Magcard Input The magcard I/O model is used to transfer synchronous serial data from an ISO 7811 Track 2 magnetic stripe card reader in real time. See the magtrack1 I/O model for track 1 compatible input, and the magcard_bitstream input model for a general-purpose magnetic card input. This model applies to Series 3100 Neuron Chips and Smart Transceivers, and to Series 5000 Neuron Processors and Smart Transceivers.
Table 33. Magcard Input Latency Values for Series 3100 Devices Symbol Description Minimum Typical Maximum tfin I/O call to first clock input — 45.0 μs — thold Data hold 0 μs — — tsetup Data setup 0 μs — — tlow Clock low width 60 μs — — thigh Clock high width 60 μs — — twto Width of timeout pulse 60 μs — — tclk Clock period 120 μs — — ttret Return from timeout 21.6 μs — 81.6 μs tret Return from function — — 301.
if the card were to stop moving in the middle of the transfer process. If a high level is detected on the I/O timeout pin, the io_in( ) function aborts. This input can be a one-shot timer counter output, an RC circuit, or a ~Data_valid signal from the card reader. A Series 3100 Neuron Chip or Smart Transceiver with a 10 MHz input clock rate can process a bit rate of up to 8334 bps (at a bit density of 75 bits per inch, this is a card speed of 111 inches per second).
// This next object allows monitoring of // the ~Data_valid input signal. IO_7 input bit ioDataValid; int nibbles; unsigned int buffer[20]; . . . when (io_changes(ioDataValid) to 0) { nibbles = io_in(ioCardData, buffer); } Magtrack1 Input The magtrack1 I/O model is used to transfer synchronous serial data from an ISO 3554 track 1 magnetic stripe card reader. See the magcard input model for track 2 compatible input, and the magcard_bitstream input model for a general-purpose magnetic card input.
Table 34. Magtrack1 Input Latency Values for Series 3100 Devices Symbol Description Minimum Typical Maximum tfin I/O call to first clock input — 45.0 μs — thold Data hold tlow — tclk tsetup Data setup 0 μs — — tlow Clock low width 31 μs — — thigh Clock high width 31 μs — — twto Width of timeout pulse 60 μs — — tclk Clock period 138 μs — — ttret Return from timeout 21.6 μs — 81.6 μs tret Return from function — — 301.
io_in( ) function. The data is stored without the parity bit, and the data includes the start and end sentinel characters. This buffer should be 78 bytes long. For magtrack1 input, the io_in( ) function requires a pointer to a data buffer, into which the series of 6-bit characters are stored. The io_in( ) function returns a signed int that contains the actual number of bytes stored. The parity of each character is checked. The LRC character, which appears just after the end sentinel, is also checked.
Example // In this example I/O pin IO_7 is connected to a // ~Data_valid signal which is asserted low as long // as a valid clock input is being generated by the // reader device. IO_8 input magtrack1 timeout(IO_7) ioCardData; // This next object allows monitoring of the // ~Data_valid input signal. IO_7 input bit ioDataValid; int read; unsigned int buffer[78]; . . .
IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7 IO8 IO9 IO10 IO11 Select Timeout Clock Data Out Data In Clock Data Out Data In IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7 IO8 IO9 IO10 IO11 Neurowire MASTER Neurowire SLAVE Figure 33. Neurowire I/O Neurowire Master Mode In Neurowire master mode, pin IO8 is the clock (driven by the Smart Transceiver), IO9 is the serial data output, and IO10 is the serial data input. Serial data is clocked out on pin IO9 at the same time as data is clocked in from pin IO10.
Table 35. Neurowire Master Output Latency Values for Series 3100 Devices Symbol Description Typical at 10 MHz tfin Function call to CS~ active 69.9 μs tret Return from function 7.2 μs thold Active clock edge to sampling of input data 20 kbps bit rate 10 kbps bit rate 1 kbps bit rate 11.4 μs 53.4 μs 960.6 μs thigh Period, clock high (active clock edge = 1) 20 kbps bit rate 10 kbps bit rate 1 kbps bit rate 25.8 μs 67.8 μs 975.0 μs tlow Period, clock low (active clock edge = 1) 33.
tfin tcklo tret tcklodo tdocki INPUT CLOCK DATA OUT DATA IN TIME CLOCK DATA CLOCK START AND DATA SAMPLED OUTPUT OF SAMPLED io_in() DATA END OF OUTPUT io_in() Figure 35. Neurowire Slave Timing Table 36. Neurowire Slave Output Latency Values for Series 3100 Devices Symbol Description Typical at 10 MHz tfin Function call to data bit out 41.4 μs tret Return from function 19.2 μs tdocki Data out to input clock and data sampled 4.8 μs tcklo Data sampled to clock low sampled 24.
5. When the input clock is low, return to step 1 if there are more bits to be processed. 6. Else return the number of bits processed. When either clock input test fails (that is, the clock is sampled before the next transition), there is an additional timeout check time of 19.8 μs (wait for clock high) or 19.2 μs (wait for clock low) added to that stage of the algorithm.
This pragma must appear prior to the use of any I/O function, such as io_in( ) or io_out( ). For examples on the use of the Neurowire input/output model, see the following engineering bulletins: Driving a Seven Segment Display with the Neuron Chip (part no. 005-0014-01) and Analog-to-Digital Conversion with the Neuron Chip (part no. 005-0019-01). Syntax IO_8 neurowire master | slave [select (pin-nbr)] [timeout (pin-nbr)] [kbaud (const-expr)] [clockedge (+|-)] io-object-name; IO_8 Specifies pin IO_8.
kbaud (const-expr) Specifies the bit rate for a Neurowire master. The expression const-expr can evaluate to 1, 10, or 20. The default is 20. The firmware uses this value as a multiplier based on the Series 3100 input clock or Series 5000 system clock. For example, for a Series 3100 device at 10 MHz, kbaud(10) yields 10 kbps; for a Series 5000 device at 10 MHz, kbaud(10) yields 20 kbps. The bit rate scales proportionally with the input or system clock. Not used for a Neurowire slave.
communication interface that is compatible with EIA-232 serial interfaces (with the exception of voltage levels). External driver hardware can be used to adjust the voltage levels. The SCI I/O model uses the UART hardware and interrupt capability in designated Neuron Chips and Smart Transceivers. You cannot use both hardware SCI and hardware SPI I/O in the same application. The hardware SCI I/O object does not include any form of hardware flow control, such as CTS/RTS flow control.
START STOP START Figure 36. SCI I/O and Timing Programming Considerations You can enable and disable SCI interrupts. For example, you can turn off interrupts when going offline, or to assure that other time-critical application functions are not disturbed by SCI interrupts. The SCI interrupt signal is used by the firmware driver for the SCI I/O object. It is not directly accessible by the application program. The SCI interrupt is enabled by default.
If you do not specify the #pragma specify_io_clock compiler directive, the compiler uses a default I/O clock rate of 10 MHz. Syntax IO_8 sci [baud (const-expr)] [twostopbits] [parity (parity-expr)] io-object-name; baud (const-expr) Optionally specifies the serial bit rate through use of the enumeration values found in the include file.
io-object-name Specifies a name for the I/O object, in the ANSI C format for variable identifiers. You can call the io_set_baud(io-obj-name, rate) function to change the bit rate for the SCI interface. The specified rate must be one of the enumeration values listed above.
Example #pragma specify_io_clock "10 MHz" IO_8 sci twostopbits baud(SCI_2400) ioSci; unsigned short buffer[20]; when (...) { io_set_baud(ioSci, SCI_38400); // Optional baud change io_out_request(ioSci, buffer, 20); } when (io_out_ready(ioSci)) { unsigned short sciError; sciError = sci_get_error(ioSci)); if (sciError) { // Process SCI error ... } else { // Process end of SCI transmission ...
START STOP START Parity is not supported for this model. The application code can use bit I/O pins for flow control handshaking if required. Figure 37. Serial Input and Timing Table 37.
START STOP START Figure 38. Serial Output Timing Table 38. Serial Output Latency Values for Series 3100 Devices Symbol Description Typical at 10 MHz tfout Function call to start bit 79 μs tret Return from function 10 μs The duration of this function call is a function of the number of data bits transferred and the transmission bit rate. For example, to output 100 bytes at 300 bits/second requires a time duration of (100 x 10 x 1/300) + tfout + tret.
• Serial input can only work successfully if the application is responsive enough to capture the start bit of the first byte received. Usually the best way to succeed with the serial input model is to employ bi-directional handshaking using two additional I/O pins, so that the sender can coordinate the transfer with the Neuron C application.
io-object-name A user-specified name for the I/O object, in the ANSI C format for variable identifiers. Usage unsigned int count, input-buffer[buffer-size], output-buffer[buffer-size]; count = io_in(io-object-name, input-buffer, count); io_out(io-object-name, output-buffer, count); Serial Input Example IO_8 input serial ioKeyboard; char buffer[20]; unsigned int chars; when (...) { chars = io_in(ioKeyboard, buffer, 20); } Serial Output Example IO_10 output serial ioDisplay; when (...
• In master mode, pin IO8 is the clock (driven by the Smart Transceiver), IO9 is serial data input (Master In Slave Out or MISO), and IO10 is serial data output (Master Out Slave In or MOSI). • In slave mode, pin IO8 is the clock input, IO9 is serial data output (MISO), and IO10 is serial data input (MOSI). The declaration of the SPI I/O object supports several modifiers, including neurowire.
Clock Bit Rate for 10 MHz Bit Rate for 6.5536 MHz Note: For Clock 5 and higher bit rates, the bit rate shown is the peak rate. The data is burst out in pairs of bytes, and the overall average data rate is limited to approximately 40 kbps and 25 kbps for 10 MHz and 6.5536 MHz input clocks, respectively. Table 40. SPI Master Mode for Series 5000 Devices Clock Bit Rate for 80 MHz Bit Rate for 40 MHz Bit Rate for 20 MHz Bit Rate for 10 MHz Bit Rate for 5 MHz 7 156.25 kbps 78.125 kbps 39.
Table 42. SPI Slave Mode for Series 5000 Devices Parameter Value for 80 MHz Value for 40 MHz Value for 20 MHz Value for 10 MHz Value for 5 MHz Max burst rate 10 Mbps 5 Mbps 2.5 Mbps 1.
[default] (CPOL = 1) Invert (CPOL = 0) Present bit Sample bit MOSI msb bit6 bit5 bit4 bit3 bit2 bit1 lsb MISO msb bit6 bit5 bit4 bit3 bit2 bit1 lsb SS Figure 39. Transmission Timing for Clockedge(-) (CPHA : 0) [default] (CPOL = 1) invert (CPOL = 0) Present bit Sample bit MOSI msb bit6 bit5 bit4 bit3 bit2 bit1 lsb MISO msb bit6 bit5 bit4 bit3 bit2 bit1 lsb SS Figure 40.
IO0 IO0 IO1 IO1 IO2 IO2 IO3 IO3 IO4 IO4 IO5 IO5 IO6 IO6 IO7 IO7 IO8 Clock IO8 Clock IO9 MISO IO9 Data Out IO10 MOSI IO10 IO11 Data In IO11 SPI Master (Neurowire pin mode) SPI Master Figure 41. SPI Master Mode I/O Select Tsc Tck Clock (invert for clockedge+ or invert=true) Tdoc Tcdo Data Out Data In Tdis Tdih Figure 42. SPI Master Mode Timing Table 44.
Symbol Description Minimum Typical Maximum Tdih Data in hold 10 ns — — IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7 Select IO8 Clock IO9 Data Out IO10 Data In IO11 SPI Slave Figure 43. SPI Slave Mode I/O Select Tsc Tck Clock (invert for clockedge- or invert=true) Tdoc Tcdo Data Out Data In Tdis Tdih Figure 44.
Table 45. SPI Slave Mode I/O Latency Values for Series 3100 Devices Symbol Description Minimum Typical Maximum Tck Clock cycle (user specified) — — 1.25 Tsc Select low to Clock transition 220 μs — — Tdoc Data out to Clock (1st bit of invert mode) 440 ns — — Tcdo Clock to data out — — 45 ns Tdis Data in setup 10 ns — — Tdih Data in hold 10 ns — — Tsdz Select high to data in high impedance — — 220 ns Programming Considerations You can enable and disable SPI interrupts.
select(IO_7) Set this option to have pin IO_7 used as a slave select (SS) signal in slave mode. In slave mode, this option is used when there are multiple slaves connected to a master. However, when the device is the only slave (and thus there is no need for the master to use a dedicated slave select signal), then pin IO_7 should be separately declared as an input pin and externally grounded. In master mode, the select keyword is not used; thus, IO_7 can be used for other purposes.
You can call the io_set_clock( ) function to change the clock divisor and clock edge at run-time. You cannot change the master/slave or Neurowire/SPI modes at run-time. io_set_clock(io-object-name, clock-value, clockedge(clock-code) ); io_set_clock(io-object-name, clock-value, clockedge(clock-code), invert); The clock-value value corresponds to the specification for the clock() keyword. For SPI slave mode devices, the clock-value should be 0.
extra bytes. For example, if a transfer is set up by the slave for 100 bytes, and there is a need to stop the transfer after 50 bytes, the interrupt driven firmware will have most likely placed bytes 51 and 52 into the SPI’s transmit hardware.
Wiegand Input The wiegand input model provides an easy interface to any card reader that supports the Wiegand interface standard. This model applies to Series 3100 Neuron Chips and Smart Transceivers, and to Series 5000 Neuron Processors and Smart Transceivers. Hardware Considerations Data from the reader is presented to the Neuron Chip or Smart Transceiver through two of its first eight I/O pins, IO0 – IO7. Up to four Wiegand devices can be connected to the Smart Transceiver.
IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7 IO8 IO9 IO10 IO11 Optional Pull-Up Resistors (3100 Family Only) t dw DATA A t ibd DATA B t fin t tow TIMEOUT t tret t ret TIME START OF io_in() END OF io_in() Figure 45. Wiegand Input and Timing Table 47. Wiegand Input Latency Values for Series 3100 Devices Symbol Description Minimum Typical Maximum tfin Function call to start of second data edge — 75.
• The zero data bit signal • A one data bit signal Data pulses appear exclusively of each other and are typically spaced approximately 1 ms apart. Specifications for the duration of the pulse are typically between 50 to 100 μs, but they can be as short as 50 ns for a Series 3100 device with a 40 MHz input clock, or 12.5 ns for a Series 5000 device with an 80 MHz system clock. Table 48 shows the pulse width and inter-bit period (the period between bit pulses). Table 48.
specification denotes the lower-numbered pin of the pair and can be IO_0 through IO_6. timeout (pin-nbr) Optionally specifies the timeout signal pin, in the range of IO_0 to IO_7. The Neuron firmware checks the logic level at this pin whenever it is waiting for a pulse at either the DATA 0 or DATA 1 pins. If a logic level 1 is sensed, the transfer is terminated. io-object-name A user-specified name for the I/O object, in the ANSI C format for variable identifiers.
5 Timer/Counter Input Models This chapter describes timer/counter input models. Timer/counter I/O models use a timer/counter circuit in the Neuron Chip or Smart Transceiver. Each Neuron Chip and each Smart Transceiver has two timer/counter circuits: One whose input can be multiplexed, and one with a dedicated input.
Introduction A Neuron Chip or Smart Transceiver has two 16-bit timer/counters: • For the first timer/counter, IO0 is used as the output, and a multiplexer selects one of pins IO4 – IO7 as the input. • The second timer/counter uses IO1 as the output and IO4 as the input. Figure 46 shows the basic timer/counter circuits for the Neuron Chip and Smart Transceiver. Figure 46. Timer/Counter Circuits A single application can declare multiple input devices that use timer/counter I/O models.
Important: The first measured value of a timer/counter is always discarded to eliminate the possibility of a bad measurement after the chip comes out of a reset condition. Single events cannot be measured with the timer/counters. Figure 47 shows an example of how the timer/counter objects are processed with a Neuron C when statement.
the input clock). Faster conversion rates are attainable at the expense of bit resolution. For a Series 3100 device, the duration of the first integration period is a function of control_value and the selected clock value: duration (ns) = control_value * 2000 * 2^(clock) / input_clock (MHz) where clock ranges from 0..
IO0 Timer/Counter 1 Control Output IO1 IO2 Timer/Counter 2 IO3 IO4 From Comparator IO5 IO6 mux IO7 IO8 IO9 IO10 IO11 OUTPUT (IO0 OR IO1) ANALOG SWITCH CONTROL INPUT (IO4 TO IO7) COMPARATOR OUTPUT INTEGRATOR OUTPUT Vthresh tfin treqo TIME START OF io_in_request() LATCHED COUNT AVAILABLE TO APPLICATION START OF io_in() END OF io_in() Figure 48. Dualslope Input and Timing Table 49.
For additional information regarding dualslope A/D conversion, see the Analog to Digital Conversion with the Neuron Chip engineering bulletin (part no. 0050019-02). Neuron C Resources The following functions and events are provided for use with the dualslope input model: io_in_request( ) Starts the first step of the integration process. The control_value argument controls the length of the first integration period. io_update_occurs Signals the end of the entire conversion process.
TCCLK_* macros defined in ). This function overrides the resolution value specified for clock() within the I/O object declaration. See Appendix A, Timer/Counter Periods and Resolution, on page 187, for a description of the timer resolution and maximum range for each specification of the clock() value or each value of the TCCLK_* macros. See the Neuron C Reference Guide for information about the io_set_clock() function.
For a Series 5000 device, this I/O model measures a series of both high and low input signal periods on a single input pin, IO_4, in units of the clock period: time_on/time_off (ns) = value_stored * 2000 * 2^(value) / 10 MHz where value ranges from 0..
Table 50. Edgelog Input Latency Values for Series 3100 Devices Symbol Description Minimum Typical Maximum tsetup Input data setup 0 — — twin Input pulse width 1 T/C clk — thold io_in() call to data input edge for inclusion of that pulse 26.4 μs — — twtcp Two consecutive pulse widths 104 μs — — toret Return on overflow — 42.6 μs — tret Return on count termination — 49.
Changes the maximum value for each period measurement for an edgelog device declared with the single_tc option keyword. The maximum value may range from 1 to 65535; the default value is 65535. Example for a Series 3100 device with a 10 MHz input clock: An edgelog input object using clock(3) and the default maximum period yields a 1.6 μs resolution and does not overflow until 104.86 ms elapse.
io-object-name A user-specified name for the I/O object, in the ANSI C format for variable identifiers. In Figure 50, an io_in( ) function call is executed sometime after the IO_4 input signal is sensed as changing to high, but before it has changed back to low. The first period, Period [1], is stored as a value in the array pointed to by the buffer argument. If the io_in( ) function call occurs within the Period [2] time frame, the data for Period [1] is lost.
// Retrieve edge log edges = io_in(ioTimeStream, buffer, 20); // Correct for preload offset for (i = 0; i < edges; i++) { buffer[i] += preLoad; } // Process data ... } Infrared Input The infrared I/O model is used to capture a data stream generated by a class of infrared remote control devices (see Figure 51 on page 135). This class of devices generates a stream of ones and zeros by modulating an infrared emitter for an on and off cycle, each cycle representing either a one or a zero.
This I/O model can be used with an off-the-shelf infrared encoder/decoder chip that uses the NEC IR protocol to quickly develop an infrared interface to a Neuron Chip or Smart Transceiver. You can also use the edgelog input model for this purpose, but your application program will likely require more code. IO0 IO1 IO2 Timer/Counter 1 Timer/Counter 2 IO3 IO4 Input Data Stream IO5 IO6 mux IO7 IO8 IO9 IO10 IO11 twin (1 BIT) INPUT (IO0 TO IO7) tret tfin TIME START OF io_in() END OF io_in() Figure 51.
• A bit_count argument, which is the expected number of data bits to be received and stored • A max_period argument limiting the range of the timer/counter measurement process • A threshold argument, representing the half way point, in timer/counter count clocks, between a zero data period and a one data period The value returned by the io_in( ) function is the actual number of bits read.
Table 52. Clock Values Range and Resolution Period Clock Series 3100 (10 MHz Clock) Series 5000 (80 MHz Clock) 0 0 to 13.11 ms in steps of 200 ns (0-65535) 0 to 1.639 ms in steps of 12.5 ns (065535) 1 0 to 26.21 ms in steps of 400 ns 0 to 3.278 ms in steps of 25 ns 2 0 to 52.42 ms in steps of 800 ns 0 to 6.555 ms in steps of 50 ns 3 0 to 104.86 ms in steps of 1.6 μs 0 to 13.11 ms in steps of 100 ns 4 0 to 209.71 ms in steps of 3.2 μs 0 to 26.21 ms in steps of 200 ns 5 0 to 419.
MHz, and the timer/counter clock is clock (7). This yields a 25.6 μs timer/counter clock resolution. The max-period parameter is set to cause an overflow at 110% of the start cycle (the timer/counter will count up from this value): ⎛ 1.10 * (9 * 10 −3 ) ⎞ ⎟⎟ 65536 − ⎜⎜ −6 ⎝ 25.6 * 10 ⎠ = 65149 Given the one and zero data periods, the threshold value is: ⎛ ⎡ (1.125 * 10 −3 ) + (2.25 * 10 −3 ) ⎤ ⎞ ⎜⎢ ⎥⎟ 2 ⎜⎣ ⎦⎟ 65149 + ⎜ ⎟ −6 25.
time_on (ns) = return_value * 2000 * 2^(value) / 10 MHz where value ranges from 0..15 You can use this model to implement digital-to-analog (D/A) converters, frequency counters, or tachometers. This model applies to Series 3100 Neuron Chips and Smart Transceivers, and to Series 5000 Neuron Processors and Smart Transceivers. Hardware Considerations A timer/counter can be configured to measure the time for which its input is asserted.
Symbol Description Typical at 10 MHz Note: If the measurement is new, tret = 52 μs. If a new time is not being returned, tret = 22 μs. Programming Considerations For ontime input, the data type of the return value for the io_in( ) function is an unsigned long. The state of the input pin is latched in hardware every 50 ns for a Series 3100 device with a 40 MHz input clock, or every 12.5 ns for a Series 5000 device with an 80 MHz system clock (the value scales inversely with clock speed).
For an application running on a Series 5000 device, you can specify an increased resolution for the timer base clock frequency by calling the io_set_clock() function with a clock value in the range 0..15 (using one of the TCCLK_* macros defined in ). This function overrides the resolution value specified for clock() within the I/O object declaration.
Hardware Considerations A timer/counter can be configured to measure the period from one rising or falling edge to the next corresponding edge on the input. The resolution and range of the timer/counter period options is described in Timer/Counter Resolution and Maximum Range on page 188. This model is useful for instantaneous frequency or tachometer applications. Analog-to-digital conversion can be implemented using a voltage-to-frequency converter with this model (see Figure 53 on page 143).
IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7 IO8 IO9 IO10 IO11 Event Register Timer/Counter 2 mux Timer/Counter 1 Event Register System Clock Divide Chain Optional Pull-Up Resistors for 3100 Family Devices INPUT TIME START TIMER COUNTER t fin START OF io_in() STOP TIMER COUNTER t ret READ TIMER/ COUNTER FLAG AND EVENT REGISTER CLEAR FLAG END OF io_in() Figure 53. Period Input and Timing Table 54.
Programming Considerations For period-input, the data type of the return-value for the io_in( ) function is an unsigned long. The input is latched every 50 ns for a Series 3100 device with a 40 MHz input clock, or every 12.5 ns for a Series 5000 device with an 80 MHz system clock. This value scales inversely with the input clock speed. If no edges occur during the measuring period, an overflow condition occurs.
io-object-name A user-specified name for the I/O object, in the ANSI C format for variable identifiers.
IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7 IO8 IO9 IO10 IO11 Event Register Timer/Counter 2 mux Timer/Counter 1 Event Register System Clock Divide Chain Optional Pull-Up Resistors for 3100 Family Devices t fin tret 0.839 s START START OF io_in() READ TIMER/ COUNTER FLAG AND EVENT REGISTER CLEAR FLAG STOP END OF io_in() Figure 54. Pulsecount Input and Timing Table 55.
The input is latched every 50 ns for a Series 3100 device with a 40 MHz input clock, or every 12.5 ns for a Series 5000 device with an 80 MHz system clock. This value scales inversely with the input clock. The value of a pulsecount input object is updated every 0.8388608 seconds and the io_update_occurs event becomes TRUE. If no edges occur during the measuring period, an overflow condition occurs. The next io_in( ) function call after the overflow has occurred will return the out-ofrange value of 0xFFFF.
Quadrature Input The quadrature I/O model is used to read a shaft or positional encoder input on two adjacent pins. You can use this model to monitor input data from shaft encoders for low-cost angular position input. This model applies to Series 3100 Neuron Chips and Smart Transceivers, and to Series 5000 Neuron Processors and Smart Transceivers. Hardware Considerations A timer/counter can be configured to count transitions of a binary Gray code input on two adjacent input pins.
IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7 IO8 IO9 IO10 IO11 Event Register Timer/Counter 2 Timer/Counter 1 Event Register Optional Pull-Up Resistors for 3100 Family Devices INPUT 1 INPUT 2 read, reset read, reset Count + 6 counts t fin t ret read, reset read, reset Count – 6 counts 2 x XIN (or CLK1) Period, Ex: 200 ns @ 10MHz (minimum time allowed between consecutive transitions) A START OF READ END OF io_in() TIMER/COUNTER io_in() FLAG AND EVENT REGISTER CLEAR FLAG B Figure 55.
Programming Considerations A signed long value is returned from the io_in( ) function, based on the change since the last input. The input is sampled every 50 ns for a Series 3100 device with a 40 MHz input clock, or every 12.5 ns for a Series 5000 device with an 80 MHz system clock. This value scales inversely with the input clock speed. For Series 3100 devices, add a #pragma enable_io_pullups directive to enable the Neuron Chip's or Smart Transceiver's built-in pull-up resistors.
Example IO_4 input quadrature ioDial; long angle = 0; when (io_update_occurs(ioDial)) { angle += input_value; // integrate angle in software } Totalcount Input The totalcount I/O model counts the number of input edges at the input pin since the last io_in( ) operation, or since initialization. Thus, this model can count external events, such as contact closures where it is important to keep an accurate running total (see Figure 47 on page 125 and Figure 57 on page 152).
IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7 IO8 IO9 IO10 IO11 Event Register Timer/Counter 2 mux Timer/Counter 1 Event Register Optional Pull-Up Resistors for 3100 Family Devices tret t fin read, reset START OF io_in() READ TIMER/ COUNTER FLAG AND EVENT REGISTER CLEAR FLAG read input_value = 4, reset END OF io_in() Figure 57. Totalcount Input and Timing Table 57.
Syntax pin [input] totalcount [mux | ded] [invert] io-object-name; pin An I/O pin. Totalcount input can specify pins IO_4 through IO_7. mux | ded Specifies whether the I/O object is assigned to the multiplexed or dedicated timer/counter. This keyword is used only when pin IO_4 is used as the input pin. The mux keyword assigns the I/O object to the multiplexed timer/counter. The ded keyword assigns the I/O object to the dedicated timer/counter.
6 Timer/Counter Output Models This chapter describes timer/counter output models. Timer/counter I/O models use a timer/counter circuit in the Neuron Chip or Smart Transceiver. Each Neuron Chip and each Smart Transceiver has two timer/counter circuits: One whose input can be multiplexed, and one with a dedicated input.
Edgedivide Output The edgedivide I/O model is used to control an output pin by toggling its logic state every output_value negative edges on an input pin. This toggling results in a acts as a frequency divider by providing an output frequency on either pin IO0 or IO1: divide-by-n*2 counter, where n is the value defined by the output_value argument. The output frequency is a divided-down version of the input frequency applied on pins IO4 – IO7.
Figure 58. Edgedivide Output and Timing Table 58. Edgedivide Output Latency Values for Series 3100 Devices Symbol Description Minimum Typical Maximum tfout Function call to start of timer — 96 μs — tfod Function to output disable — 82.
Symbol Description Minimum Typical Maximum tret Return from function — 13 μs — Programming Considerations For edgedivide output, the data type of the output value for io_out( ) is an unsigned long. Following reset of the Neuron Chip or Smart Transceiver, the divider is disabled until the first call to the io_out( ) function. The first call to the io_out( ) function for the edgedivide output model sets the output pin high and starts the divider.
Example IO_0 output edgedivide sync(IO_4) ioDivider; ... when (reset) { // There is a 60Hz signal at pin IO_4. // Set up the divider to produce // a change on pin IO_0 once a minute. io_out(ioDivider, 3600UL); } Frequency Output For Series 3100 devices, the frequency I/O model produces a repeating square wave output signal whose period is a function of output_value and the selected clock value: period (ns) = (output_value+n) * 4000 * 2^(clock)/ input_clock (MHz) where clock ranges from 0..
IO0 Timer/Counter 1 IO1 IO2 Timer/Counter 2 IO3 IO4 IO5 IO6 IO7 IO8 System Clock Divide Chain IO9 IO10 IO11 High Current Sink Drivers Figure 59. Frequency Output ONE CYCLE tfout FREQUENCY OUTPUT TIME tret START OF io_out() END OF io_out() NEW OUTPUT APPEARS ON PIN HARDWARE UPDATED INTERNALLY Figure 60. Frequency Output Timing Table 59.
Syntax pin [output] frequency [invert] [clock (const-expr)] io-object-name [=initialoutput-level]; pin Specifies either pin IO_0 (using the multiplexed timer/counter) or IO_1 (using the dedicated timer/counter). invert This keyword inverts the output for an output value of 0. The default output for 0 is low. clock (const-expr) Specifies a clock in the range 0 to 7, where 0 represents the fastest clock and 7 represents the slowest clock. The default value is clock 0.
when (...) { io_out(ioAlarm, 100); // outputs 3.125kHz signal at clock(3) } when (...) { io_out(ioAlarm, 50); // outputs 6.25kHz signal at clock(3) } when (...) { io_out(ioAlarm, 0); // output signal is stopped } Infrared Pattern Output An infrared_pattern I/O model produces a series of timed repeating square wave output signals. The frequency of the square wave output is controlled by the application. Normally, this frequency is the modulation frequency used for infrared transmission.
Programming Considerations The frequency of the square wave output is controlled by the clock-expr setting and by the unsigned long output-frequency value passed to the io_out( ) function. The pattern of this modulation frequency is controlled by an array of unsigned long timing values, also passed to the io_out( ) function: • The first value in this array controls the length of the first burst of modulation frequency signal output—the output is active for this period.
element of the timing-table controls the last active period before toggling to idle (off) and returning from the io_out( ) function. If the number of elements in the timing table is even, the output will be toggled on at the end of the io_out( ) function, which is typically not the desired behavior. Syntax pin [output] infrared_pattern [invert] [clock(clock-expr)] io-object-name [= initialoutput-level] ; pin Specifies a Neuron output pin. The value can be IO_0 or IO_1.
io-object-name Specifies a name for the I/O object, in the ANSI C format for variable identifiers. initial-output-level A constant expression, in ANSI C format for initializers, used to set the state of the output pin of the I/O object at initialization. The initial state is limited to 0 or 1. The default is 0. Usage unsigned count; unsigned long output-frequency, timing-table[count]; io_out(io-object-name, output-frequency, timing-table, count); (There is no return value for the function.
the oneshot before the end of the pulse causes it to continue for the new duration. The resolution and range of the timer/counter period options is described in Timer/Counter Resolution and Maximum Range on page 188. This object is useful for generating a time delay without intervention of the application processor (see Figure 62). While the output is still active, a subsequent call to this function cause the update to take effect immediately, extending the current cycle.
Symbol Description Typical at 10 MHz Note: The maximum value for tjit is 1 timer/counter clock period. Programming Considerations The oneshot I/O model can be retriggered. A call to the io_out( ) function for a oneshot object starts a new pulse, even if one is currently in progress. For oneshot output, the data type of the output value for the io_out( ) function is an unsigned long. An output value of zero (0) forces the output to a low state.
initial-output-level A constant expression, in ANSI C format for initializers, used to set the state of the output pin of the I/O object at initialization. The initial state can be 0 or 1. The default is 0. Usage unsigned long output-value; io_out(io-object-name, output-value); Example IO_0 output oneshot ioFlash; unsigned long pulse = 39062; // 1 second pulse mtimer repeating flashTimer; when (...
Output on page 190 for the frequency of the waveform for various clock select values. This model is useful for external counting devices that can accumulate pulse trains, such as stepper motors (see Figure 63). The io_out( ) function does not return until all output pulses have been produced. tfout is the time from function call to first output pulse.
Programming Considerations The output_value determines the number of pulses output. When this I/O model is used, the io_out( ) function call does not return until all pulses have been produced. This process ties up the application processor for the duration of the pulsecount. For pulsecount output, the data type of the output value for the io_out( ) function is an unsigned long. An output value of 0 forces the output signal to its normal state.
Example IO_1 output pulsecount ioTrainOut; when (...) { // will produce 100 pulses on pin 1 // each pulse of period 6.
• If the output is disabled, the new (non-zero) output starts immediately after tfout • For a new output value of zero, the output is disabled immediately and not at the end of the current cycle A disabled output is a logic 0 by default, unless the invert keyword is used in the I/O object declaration.
Programming Considerations For 8-bit pulsewidth output, the data type of output-value for the io_out( ) function is an unsigned short. An output-value of 0 results in a 0% duty cycle. A value of 255 (the maximum value allowed) results in a 100% duty cycle. The duty cycle of the pulse train is (output-value/256), except when output-value is 255; in that case, the duty cycle is 100%. For 16-bit pulsewidth output, the data type of output-value for the io_out( ) function is an unsigned long.
Usage unsigned int output-value; // for 8-bit output unsigned long output-value; // for 16-bit output io_out(io-object-name, output-value); Example IO_1 output pulsewidth clock(7) ioDimmer; mtimer repeating tick; unsigned short brightness; when (...
Figure 65. Series 3100 Triac Output Figure 66 on page 176 shows basic triac operation for a Series 5000 device using the stretchedtriac I/O object. For a Series 5000 device, the turn-on pulse has a programmatically controlled duration. By increasing the turn-on pulse duration, the stretchedtriac I/O object can control triac devices that run under highly inductive loads.
Figure 66. Series 5000 Stretched Triac Output Hardware Considerations On a Smart Transceiver, a timer/counter can be configured to control the delay of an output signal with respect to a synchronization input. This synchronization can occur on the rising edge, the falling edge, or both the rising and falling edges of the input signal. For control of AC circuits using a triac device, the sync input is typically a zero-crossing signal, and the pulse output is the triac trigger signal.
The output gate pulse is asserted after the control period and is deasserted at or near the next sync input point. Although the input trigger signal (zero crossing) is asynchronous relative to the internal clock, there is minimal jitter, tjit, associated with the output gate pulse. The actual active edge of the sync input and the triac gate output can be set by using the clockedge or invert parameters, respectively.
Syntax pin [output] stretchedtriac sync (pin-nbr) [clockedge (+)|(-)|(+-)] frequency(value) io-object-name; pin An I/O pin. Stretched triac output can specify pins IO_0 or IO_1. If IO_0 is specified, the sync pin can be IO_4 through IO_7. If IO_1 is specified, the sync pin must be IO_4. sync (pin-nbr) Specifies the sync pin, which is the input trigger signal. clockedge (+)|(-)|(+-) (+) Causes the sync input to be positive-edge sensitive. (-) Causes the sync input to be negative-edge sensitive.
• Operate at a non-standard power line frequency • Provide higher-than-typical tolerances to changes in frequency The application can determine the current values for frequency at runtime, and use this function to adjust the triac on-time as needed. Example IO_0 output stretchedtriac sync (IO_5) frequency(60) ioTriac; when (...) { io_out(ioTriac, 160); } // full on when (...) { io_out(ioTriac, 80); } // half on when (...
The actual active edge of the sync input and the triac gate output can be set by using the clockedge or invert parameters, respectively. Figure 68. Triac Output and Timing The hardware update does not happen until the occurrence of an external active sync clock edge. The internal timer is then enabled, and a triac gate pulse is generated after the user-defined period has elapsed. This sequence is repeated indefinitely until another update is made to the triac gate pulse delay value.
equivalent of an OFF state. When using the level output configuration, there is always some amount of output signal; use an output value that is about 95% of the half-cycle period to approximate the OFF state. Syntax pin [output] triac [pulse] sync (pin-nbr) [invert] [clock (const-expr)] [clockedge (+)|(-)|(+-)] io-object-name; pin An I/O pin. Triac output can specify pins IO_0 or IO_1. If IO_0 is specified, the sync pin can be IO_4 through IO_7. If IO_1 is specified, the sync pin must be IO_4.
checks for the availability of this feature. This code logs an error if the chip does not support the feature. io-object-name A user-specified name for the I/O object, in the ANSI C format for variable identifiers. [pulse] Specifies that the output signal produces a 25 μs pulse at the delay point. The output pulse is generated by an internal clock with a constant period of 25.6 μs (independent of the Neuron input clock).
Figure 69. Triac Output, Example 1 Example 2 This example does not apply to model 0 Neuron 3150 Chips. IO_1 output triac sync (IO_4) clockedge (+-) io_dimmer_2; ... io_out(io_dimmer_2,325); Figure 70. Triac Output, Example 2 Triggered Count Output You can use this I/O model to control stepper motors or position actuators that provide position feedback in the form of a pulse train.
This model applies to Series 3100 Neuron Chips and Smart Transceivers, and to Series 5000 Neuron Processors and Smart Transceivers. Hardware Considerations A timer/counter can be configured to generate an output pulse that is asserted under program control, and de-asserted when a programmable number of input edges (up to 65535) has been counted on an input pin (IO4 – IO7). Assertion can be either logic high or logic low.
Table 65. Triggered Count Output Latency Values for Series 3100 Devices Symbol Description Typical at 10 MHz tfout Function call to output update 109 μs tcod Last negative sync Clock edge to output inactive min 550 ns max 750 ns tret Return from function 7 μs Programming Considerations The triggeredcount I/O model is used to control an output pin to the active state and keep it active until output-value negative edges are counted at the input sync pin.
In Figure 72, an io_out( ) function call is executed with a count argument of 11. After 11 negative edges at the input pin, the output goes low. The delay from the last input edge to the output falling edge is 50 ns or less for a Series 3100 device with an input clock of 40 MHz, or 12.5 ns or less for a Series 5000 device with an 80 MHz system clock. Figure 72.
A Timer/Counter Periods and Resolution This appendix describes resolution, range, rate, frequency, and period information that is common to several timer/counter I/O models.
Timer/Counter Resolution and Maximum Range Various combinations of I/O pins can be configured as basic inputs or outputs. The application program can optionally specify the initial values of basic outputs. Pins configured as outputs can also be read as inputs, returning the value last written. The gradient behavior of the timing numbers for different Neuron Chip or Smart Transceiver pins for some of the I/O models is due to the shift-and-mask operation performed by the Neuron system firmware.
7 25.6 μs 1678 ms 51.2 μs 3355 ms To Calculate for Other Clock Rates: • Resolution = 2 ( ClockSelect + n ) InputClock ClockSelect = 0..7 n = 1 for dualslope, edgelog, oneshot output, ontime, period input, and triac output n = 2 for frequency output InputClock in MHz Resolution in seconds • Maximum Range = 65535 x Resolution Resolution in seconds Maximum Range in seconds For each of the timer/counter I/O models, the range and resolution in Table 66 should be read as: • Range of 13.
Table 67. Series 5000 Timer/Counter Resolution and Maximum Range Dualslope, Edgelog, Ontime, and Period Inputs; Oneshot and Triac Outputs Frequency Output TCCLK Macro Resolution Maximum Range Resolution Maximum Range TCCLK_40MHz 25 ns 1.64 ms 50 ns 3.28 ms TCCLK_20MHz 50 ns 3.28 ms 0.1 μs 6.56 ms TCCLK_10MHz 0.1 μs 6.56 ms 0.2 μs 13.1 ms TCCLK_5MHz 0.2 μs 13.1 ms 0.4 μs 26.2 ms TCCLK_2500kHz 0.4 μs 26.2 ms 0.8 μs 52.4 ms TCCLK_1250kHz 0.8 μs 52.4 ms 1.
Series 3100 Square Wave Output For pulsewidth short output and pulsecount output, Table 68 lists the possible choices for pulsetrain repetition frequencies for a Series 3100 device. Pulsecount cannot be used with clock select 0. The table lists the values for a 10 MHz input clock (the values scale for other clock rates). Table 68.
Series 5000 Square Wave Output For pulsewidth short output and pulsecount output, Table 69 lists the possible choices for pulsetrain repetition frequencies for a Series 5000 device. The resolution and range values in Table 69 apply to all system clock settings, that is, they do not scale with changes to the system clock.
Timer/Counter Pulsetrain Output The following sections list the possible choices for pulsetrain repetition frequencies for pulsewidth short output and pulsecount output. Series 3100 Pulsetrain Output For pulsewidth long output, Table 70 lists the possible choices for pulsetrain repetition frequencies. The table lists the values for a Series 3100 device with a 10 MHz input clock (the values scale for other clock rates). Table 70.
If you specify an alternate clock value (using the io_set_clock() function with a TCCLK_* macro value) that is lower than your device’s system clock setting, the resolution and range values reflect the expected values specified in Table 71. However, you cannot specify a value that defines a clock rate that is higher than one-half of the device’s system clock.
Index # #pragma codegen use_i2c_version_1, 83 #pragma enable_io_pullups, 10 #pragma enable_multiple_baud, 96, 106 #pragma specify_io_clock, 100 event I/O, 22 io_changes, 22 io_in_ready, 71 io_out_ready, 71 io_update_occurs, 23, 128 F 1 1-Wire protocol, 43 3 3554 device, 89 7 7811 device, 86 A A/D converter, 125 angular position measurement, 148 ASCII data, 35 B BCD data, 40 bit I/O, 32 bitshift I/O, 76 byte I/O, 35 C CPHA, 110 CPOL, 110 crc16 function, 49 crc8 function, 49 D D/A converters, 138, 14
I I/O A/D converter, 125 angular position measurement, 148 ASCII data, 35 BCD data, 40 D/A converter, 138, 141, 165, 171 EIA-232, 103 eight pin, 35 frequency counter, 138, 141 frequency divider, 156 frequency measurement, 168 infrared command input, 129 infrared remote control, 134, 162 lamp dimmer, 174, 179 latched, 38 LCD display, 103 magnetic card reader, 84, 86 magnetic stripe reader, 89 measurements, 28 modem, 103 parallel, 55 position actuator, 183 running total, 151 shaft encoder, 148 shift register,
L lamp dimmers, 174, 179 latch, 38 latency function call, 15 scheduler, 13 LCD displays, 103 leveldetect input, 38 pragma enable_io_pullups, 10 pragma enable_multiple_baud, 96, 106 pragma specify_io_clock, 100 programming considerations, 15 pull-ups, enabling, 10 pulsecount input, 145 pulsecount output, 168 pulsetrain output, timer/counter, 193 pulsewidth output, 171 M magcard bitstream input, 84 magcard input, 86 magnetic card reader, 84, 86 magnetic stripe reader, 89 magtrack1 input, 89 measurements, I/
token passing, 66 totalcount input, 151 touch I/O, 43 touch_bit function, 48 touch_byte function, 48 touch_byte_spu function, 49 touch_first function, 48 touch_next function, 48 touch_read_spu function, 49 touch_reset function, 47 touch_reset_spu function, 49 touch_write_spu function, 49 triac device, 174, 179 triac output, 179 triggered count output, 183 tst_bit function, 136 198 TTL signals, 32 U UART, 52, 98 V variable input_is_new, 21 input_value, 24 W Wiegand input, 118 Index
www.echelon.
