Instruction Manual

General-Purpose Registers
The Neuron architecture defines 16 hardware memory locations that the Neuron
Assembler uses as general-purpose registers, typically named R0, R1, R2, and so
on, to R15, as described in Table 6. Each of the general-purpose registers is
eight bits wide.
Table 6. General-Purpose Registers
General-
Purpose
Register
Description
R0 Scratch register. A function can use this register as needed.
Assume that any call to the firmware, or to any function in a
library or written in Neuron C, might change the contents of
this register.
R1 Scratch register. A function can use this register as needed.
Assume that any call to the firmware, or to any function in a
library or written in Neuron C, might change the contents of
this register.
R2 Scratch register. A function can use this register as needed.
Assume that any call to the firmware, or to any function in a
library or written in Neuron C, might change the contents of
this register.
R3 Reserved for use by the system firmware.
R4 Reserved for use by the system firmware.
R5 Reserved for use by the system firmware.
R6 Reserved for use by the system firmware.
R7 Reserved for use by the system firmware.
R8 Reserved for use by the system firmware.
R9 Reserved for use by the system firmware.
R10 Reserved for use by the system firmware.
R11 Reserved for use by the system firmware.
R12 Reserved for use by the system firmware.
R13 Reserved for use by the system firmware.
R14 Reserved for use by the system firmware.
R15 Reserved for use by the system firmware.
18 Neuron Architecture for Neuron Assembly Programming