Service manual

DCB, DCFCB and DCFCTB Models
39
Theory of Operation
through which C4 is charged to 4.0 Volts, and this voltage is applied to the non-
inverting input of IC2B and the inverting input of IC2A. The output of the current
sensor is linearly scaled such that a change of 100 Amps in sensed current results
in a change of 1.0 Volt at the output, and a change of 1.0 Amp results in a change
of 0.01 Volts at the output. Using this calibration, POT1 and POT2 can be
adjusted to set upper and lower current thresholds, respectively.
A typical application of the current sensor could be to set the device for an upper
current threshold of 300 Amps, and a lower current threshold of 50 Amps. Using
these values, the voltage at TP1 corresponding to 150 Amps is the following:
4.0V + (300A * 0.01V/A) = 7V
The voltage at TP1 corresponding to 70 Amps is the following:
4.0V + (50A * 0.01V/A) = 4.5V
Adjusting POT1 sets the upper current threshold voltage of 7V at TP2, and
adjusting POT2 sets the lower current threshold voltage of 4.5 V at TP4. With a
sensed current value between 50 and 300 Amps, the voltage at TP1 is between 4.5
and 7 Volts. Since the voltage at the inverting input of IC2B (pin 6, also TP2) is
set to 7 Volts, and the voltage at the non-inverting input (pin 5) is less than 7
Volts, the output of IC2B (pin 7) is logic low. Similarly, since the voltage at the
non-inverting input of IC2A (pin3, also TP4) is set to 4.5 Volts, and the voltage at
the inverting input (pin 2) is greater than 4.5 Volts, the output of IC2A (pin 1) is
also logic low.
The outputs of IC2A and IC2B are applied directly to the inputs of NOR gate IC3.
With a logic low at both inputs of IC3 (pins 1 and 2), the output of IC3 at pin 3 is
a logic high, approximately 8 Volts. 8 Volts applied through R1 to the input (pin
1) of opto-coupler IC4 causes the output transistor of IC4 to be saturated and a
logic low is applied to J1-2, indicating that the sensed current is within the preset
acceptable range.
In the case that the sensed current exceeds the upper current limit, the voltage at
TP1 is larger than 7 Volts, putting the non-inverting input of IC2B at a higher
potential than the inverting input, resulting in a logic high at the output of IC2B,
which is applied to pin 1 of IC3. A logic high at either or both inputs of IC3 yields
a logic low at the output of IC3, which causes the output transistor of IC4 to be
cut off and a logic high is applied to J1-2, indicating that the sensed current is
outside the acceptable range. J2-1 must be pulled high by whatever circuit it is
connected to. In similar fashion, if the sensed current falls below the lower current
limit, the voltage at TP1 is less than 4.5 Volts, putting the inverting input at a
lower potential than the non-inverting input, resulting in a logic high at the output
of IC2A, which is applied to pin 2 of NOR gate IC3. As described above, this