nRF52832 Product Specification v1.3 Key features • 2.4 GHz transceiver Applications • Internet of Things (IoT) • -96 dBm sensitivity in Bluetooth® low energy mode • • 2 Mbps Bluetooth® low energy mode • 1 Mbps, 2 Mbps supported data rates • • • • • TX power -20 to +4 dBm in 4 dB steps • Single-pin antenna interface • 5.3 mA peak current in TX (0 dBm) • 5.
Contents Contents 1 Revision history 2 About this document 9 10 2.1 Peripheral naming and abbreviations.............................................................................................10 2.2 Register tables 10 2.3 Registers 11 3 Block diagram 4 Pin assignments 4.1 QFN48 pin assignments 4.2 WLCSP ball assignments 4.3 GPIO usage restrictions 12 13 13 15 17 5 Absolute maximum ratings 19 6 Recommended operating conditions......................................................................
Contents 16 Debug and trace 72 17 Power and clock management 76 16.1 16.2 16.3 16.4 16.5 DAP - Debug Access Port CTRL-AP - Control Access Port Debug interface mode Real-time debug Trace 17.1 Current consumption scenarios 18 POWER — Power supply 18.1 Regulators 18.2 System OFF mode 18.3 System ON mode 18.4 Power supply supervisor 18.5 RAM sections 18.6 Reset 18.7 Retained registers 18.8 Reset behavior 18.9 Registers 18.
Contents 24.3 24.4 24.5 24.6 Task delays Task priority Registers Electrical specification 235 235 235 241 25 RTC — Real-time counter 242 25.1 Clock source 242 25.2 Resolution versus overflow and the PRESCALER..................................................................242 25.3 COUNTER register 243 25.4 Overflow features 243 25.5 TICK event 243 25.6 Event control feature 244 25.7 Compare feature 244 25.8 TASK and EVENT jitter/delay 246 25.9 Reading the COUNTER register 248 25.10 Registers 248 25.
Contents 32 SPIS — Serial peripheral interface slave with EasyDMA.................................. 292 32.1 32.2 32.3 32.4 32.5 32.6 Shared resources EasyDMA SPI slave operation Pin configuration Registers Electrical specification 292 292 293 294 295 303 33.1 33.2 33.3 33.4 33.5 33.6 33.7 33.8 33.
Contents 37.8 Reference 37.9 Acquisition time 37.10 Limits event monitoring 37.11 Registers 37.12 Electrical specification 37.13 Performance factors 363 363 364 365 389 391 38.1 38.2 38.3 38.4 38.5 38.6 Shared resources Differential mode Single-ended mode Pin configuration Registers Electrical specification 393 393 394 396 396 401 39.1 39.2 39.3 39.4 Shared resources Pin configuration Registers Electrical specification 40.1 40.2 40.3 40.4 40.
Contents 44.8 Module operation 44.9 Pin configuration 44.10 Registers 44.11 Electrical specification 452 453 454 461 45.1 Registers 462 45 MWU — Memory watch unit 462 46 EGU — Event generator unit 489 46.1 Registers 46.2 Electrical specification 489 495 47 PWM — Pulse width modulation 496 47.1 47.2 47.3 47.4 47.5 47.6 Wave counter Decoder with EasyDMA Limitations Pin configuration Registers Electrical specification 496 499 504 504 505 513 48 SPI — Serial peripheral interface master.............
Contents 53.6 Schematic CIAA WLCSP with DC/DC regulator and NFC setup.......................................... 551 53.7 PCB guidelines 551 53.8 PCB layout example 552 54 Liability disclaimer 54.1 RoHS and REACH statement 54.
1 Revision history 1 Revision history Date February 2017 Version 1.3 Description The following content has been added or updated: • September 2016 RADIO — 2.4 GHz Radio on page 205: Introduced 2 Mbps Bluetooth® low energy mode. • FICR — Factory information configuration registers on page 43: Updated INFO.PACKAGE register (new package added). • UARTE: Corrected the pin configuration table. • PPI — Programmable peripheral interconnect on page 168: Timing information corrected.
2 About this document 2 About this document This Product Specification is organized into chapters based on the modules and peripherals that are available in this IC. The peripheral descriptions are broken into separate sections that include the following information: • • • A detailed functional description of the peripheral.
2 About this document 2.3 Registers Table 1: Register Overview Register Offset Description DUMMY 0x514 Example of a register controlling a dummy feature 2.3.
3 Block diagram 3 Block diagram This block diagram illustrates the overall system. Arrows with white heads indicate signals that share physical pins with other signals. SWCLK GPIO RAM 7 P0 (P0.0 – P0.
4 Pin assignments 4 Pin assignments Here we cover the pin assignments for each variant of the chip. 4.1 QFN48 pin assignments P0.25 P0.26 P0.27 P0.28/AIN4 P0.29/AIN5 P0.30/AIN6 P0.31/AIN7 NC VSS DEC4 DCC VDD 37 38 39 40 41 42 43 44 45 46 47 48 DEC1 P0.00/XL1 P0.01/XL2 P0.02/AIN0 P0.03/AIN1 P0.04/AIN2 P0.05/AIN3 P0.06 P0.07 P0.08 NFC1/P0.09 NFC2/P0.
4 Pin assignments Pin Name Type Description 10 P0.08 Digital I/O General purpose I/O 11 NFC1 NFC input NFC antenna connection P0.09 Digital I/O General purpose I/O1 NFC2 NFC input NFC antenna connection P0.10 Digital I/O General purpose I/O1 13 VDD Power Power supply 14 P0.11 Digital I/O General purpose I/O 15 P0.12 Digital I/O General purpose I/O 16 P0.13 Digital I/O General purpose I/O 17 P0.
4 Pin assignments Pin Name 44 NC Type Description No connect Leave unconnected 45 VSS Power Ground 46 DEC4 Power 1.3 V regulator supply decoupling Input from DC/DC regulator Output from 1.3 V LDO 47 DCC Power DC/DC regulator output 48 VDD Power Power supply VSS Power Ground pad Bottom of chip Die pad Exposed die pad must be connected to ground (VSS) for proper device operation. 4.
4 Pin assignments Ball Name B4 P0.27 Digital I/O General purpose I/O3 B5 P0.31 Digital I/O General purpose I/O3 AIN7 Analog input SAADC/COMP/LPCOMP input B6 DCC Power DC/DC converter output B7 DEC1 Power 0.9 V regulator digital supply decoupling C2 DEC3 Power Power supply decoupling C3 NC N/A Not connected C4 VSS Power Ground C5 VSS Power Ground C6 P0.02 Digital I/O General purpose I/O AIN0 Analog input SAADC/COMP/LPCOMP input P0.
4 Pin assignments Ball Name Description TRACEDATA[2] H5 P0.14 Trace port output Digital I/O TRACEDATA[3] General purpose I/O Trace port output H6 P0.12 Digital I/O General purpose I/O H7 VDD Power Power supply 4.3 GPIO usage restrictions 4.3.1 GPIO located near the radio Radio performance parameters, such as sensitivity, may be affected by high frequency digital I/O with large sink/source current close to the Radio power supply and antenna pins.
4 Pin assignments For information on how to configure these pins as normal GPIOs, see NFCT — Near field communication tag on page 417 and UICR — User information configuration registers on page 54. Note that the device will not be protected against strong NFC field damage if the pins are configured as GPIO and an NFC antenna is connected to the device. The pins will always be configured as NFC pins during power-on reset until the configuration is set according to the UICR register.
5 Absolute maximum ratings 5 Absolute maximum ratings Maximum ratings are the extreme limits to which the chip can be exposed for a limited amount of time without permanently damaging it. Exposure to absolute maximum ratings for prolonged periods of time may affect the reliability of the device. Table 7: Absolute maximum ratings Supply voltages VDD VSS I/O pin voltage VI/O , VDD ≤3.6 V VI/O , VDD >3.
6 Recommended operating conditions 6 Recommended operating conditions The operating conditions are the physical parameters that the chip can operate within. Table 8: Recommended operating conditions Symbol VDD tR_VDD TA Parameter Supply voltage, independent of DCDC enable Supply rise time (0 V to 1.7 V) Operating temperature Notes Min. 1.7 Nom. 3.0 -40 25 Max. 3.
7 CPU 7 CPU The ARM® Cortex®-M4 processor with floating-point unit (FPU) has a 32-bit instruction set (Thumb®-2 technology) that implements a superset of 16 and 32-bit instructions to maximize code density and performance.
7 CPU Symbol Description CM FLASH CoreMark5, running from flash, cache enabled Min. Typ. 215 Max. Units CoreMark CM FLASH/MHz CoreMark per MHz, running from flash, cache enabled 3.36 CoreMark/ CM FLASH/mA CoreMark per mA, running from flash, cache enabled, DCDC 3V 58 MHz CoreMark/ mA 7.3 CPU and support module configuration The ARM® Cortex®-M4 processor has a number of CPU options and support modules implemented on the device.
8 Memory 8 Memory The nRF52832 contains flash and RAM that can be used for code and data storage. The amount of RAM and flash will vary depending on variant, see Table 9: Memory variants on page 23. Table 9: Memory variants Device name nRF52832-QFAA nRF52832-QFAB nRF52832-CIAA RAM 64 kB 32 kB 64 kB Flash 512 kB 256 kB 512 kB Comments The CPU and the EasyDMA can access memory via the AHB multilayer interconnect.
8 Memory 8.2 Flash - Non-volatile memory The Flash can be read an unlimited number of times by the CPU, but it has restrictions on the number of times it can be written and erased and also on how it can be written. Writing to Flash is managed by the Non-volatile memory controller (NVMC), see NVMC — Non-volatile memory controller on page 29. The Flash is divided into multiple pages that can be accessed by the CPU via both the ICODE and DCODE buses as shown in, Figure 4: Memory layout on page 23.
8 Memory ID Base Address Peripheral Instance Description 3 0x40003000 TWIS TWIS0 Two-wire interface slave 0 4 0x40004000 SPIM SPIM1 SPI master 1 4 0x40004000 TWI TWI1 Two-wire interface master 1 4 0x40004000 SPIS SPIS1 SPI slave 1 4 0x40004000 TWIS TWIS1 Two-wire interface slave 1 4 0x40004000 TWIM TWIM1 Two-wire interface master 1 4 0x40004000 SPI SPI1 SPI master 1 5 0x40005000 NFCT NFCT Near Field Communication Tag 6 0x40006000 GPIOTE GPIOTE GPIO Tasks and
9 AHB multilayer 9 AHB multilayer The CPU and all of the EasyDMAs are AHB bus masters on the AHB multilayer, while the RAM and various other modules are AHB slaves. See Block diagram on page 12 for an overview of which peripherals implement EasyDMA. The CPU has exclusive access to all AHB slaves except for the RAM that can also be accessed by the EasyDMA.
10 EasyDMA 10 EasyDMA EasyDMA is an easy-to-use direct memory access module that some peripherals implement to gain direct access to Data RAM. The EasyDMA is an AHB bus master similar to the CPU and it is connected to the AHB multilayer interconnect for direct access to the Data RAM. The EasyDMA is not able to access the Flash.
10 EasyDMA 0x20000000 readerBuffer[0] readerBuffer[1] readerBuffer[2] readerBuffer[3] 0x20000004 readerBuffer[4] writerBuffer[0] writerBuffer[1] writerBuffer[2] 0x20000008 writerBuffer[3] writerBuffer[4] writerBuffer[5] Figure 7: EasyDMA memory layout The EasyDMA channel's MAXCNT register cannot be specified larger than the actual size of the buffer. If, for example, the WRITER.
11 NVMC — Non-volatile memory controller 11 NVMC — Non-volatile memory controller The Non-volatile memory controller (NVMC) is used for writing and erasing the internal Flash memory and the UICR. Before a write can be performed, the NVMC must be enabled for writing in CONFIG.WEN. Similarly, before an erase can be performed, the NVMC must be enabled for erasing in CONFIG.EEN, see CONFIG on page 31. The user must make sure that writing and erasing are not enabled at the same time.
11 NVMC — Non-volatile memory controller 11.5 Erase all When erase is enabled, the whole Flash and UICR can be erased in one operation by using the ERASEALL register. ERASEALL will not erase the factory information configuration registers (FICR). The time it takes to perform an ERASEALL command is specified by tERASEALL The CPU is halted while the NVMC performs the erase operation. 11.6 Cache An instruction cache (I-Cache) can be enabled for the ICODE bus in the NVMC.
11 NVMC — Non-volatile memory controller Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id A Reset 0x00000000 Id RW Field A R 0 Value Id 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value READY Description NVMC is ready or busy Busy 0 NVMC is busy (on-going write or erase operation) Ready 1 NVMC is ready 11.7.
11 NVMC — Non-volatile memory controller Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id A Reset 0x00000000 Id RW Field A RW ERASEALL 0 Value Id 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Description Erase all non-volatile memory including UICR registers. Note that code erase has to be enabled by CONFIG.EEN before the UICR can be erased. NoOperation 0 No operation Erase 1 Start chip erase 11.7.
11 NVMC — Non-volatile memory controller Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id Reset 0x00000000 Id RW Field A RW HITS 0 Value Id AA A A A A A A AAAA A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Description Number of cache hits 11.7.10 IMISS Address offset: 0x54C I-Code cache miss counter.
12 BPROT — Block protection 12 BPROT — Block protection The mechanism for protecting non-volatile memory can be used to prevent application code from erasing or writing to protected blocks. Non-volatile memory can be protected from erases and writes depending on the settings in the CONFIG registers. One bit in a CONFIG register represents one protected block of 4 kB. There are four CONFIG registers of 32 bits, which means there are 128 protectable blocks in total.
12 BPROT — Block protection 12.1.
12 BPROT — Block protection Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id f e d c b a Z Y XWVU T S R Q P O N M L K J Reset 0x00000000 0 0 0 0 0 0 0 0 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Id RW Field R RW REGION17 S T U V W X Y Z a b c d e f Value Id Value Description Enabled 1 Protection enable Disabled 0 Protection disabled Enabled 1 Protection enable Disabled 0 Protection disabled Enabled 1 Protec
12 BPROT — Block protection Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id f e d c b a Z Y XWVU T S R Q P O N M L K J Reset 0x00000000 0 0 0 0 0 0 0 0 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Id RW Field A RW REGION32 B C D E F G H I J K L M N O P Q R S Value Id Value Disabled 0 Protection disabled Enabled 1 Protection enabled Disabled 0 Protection disabled Enabled 1 Protection enabled Disabled 0 Prot
12 BPROT — Block protection Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id f e d c b a Z Y XWVU T S R Q P O N M L K J Reset 0x00000000 0 0 0 0 0 0 0 0 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Id T U V W X Y Z a b c d e f RW Field Value Id Value Description Disabled 0 Protection disabled Enabled 1 Protection enabled Disabled 0 Protection disabled Enabled 1 Protection enabled Disabled 0 Protection disabled E
12 BPROT — Block protection Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id A Reset 0x00000001 Id RW Field 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Value Id Value Enabled 0 Description Enable in debug 12.1.
12 BPROT — Block protection Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id f e d c b a Z Y XWVU T S R Q P O N M L K J Reset 0x00000000 0 0 0 0 0 0 0 0 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Id RW Field P RW REGION79 Q R S T U V W X Y Z a b c d e f Value Id Value Description Enabled 1 Protection enabled Disabled 0 Protection disabled Enabled 1 Protection enabled Disabled 0 Protection disabled Enabled 1
12 BPROT — Block protection 12.1.
12 BPROT — Block protection Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id f e d c b a Z Y XWVU T S R Q P O N M L K J Reset 0x00000000 0 0 0 0 0 0 0 0 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Id RW Field R RW REGION113 S T U V W X Y Z a b c d e f Value Id Value Description Enabled 1 Protection enabled Disabled 0 Protection disabled Enabled 1 Protection enabled Disabled 0 Protection disabled Enabled 1 Pro
13 FICR — Factory information configuration registers 13 FICR — Factory information configuration registers Factory information configuration registers (FICR) are pre-programmed in factory and cannot be erased by the user. These registers contain chip-specific information and configuration. 13.
13 FICR — Factory information configuration registers Register Offset Description NFC.TAGHEADER0 0x450 Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFC.TAGHEADER1 0x454 NFC.TAGHEADER2 0x458 NFC.TAGHEADER3 0x45C NFCID1_2ND_LAST and NFCID1_LAST. Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. Default header for NFC Tag.
13 FICR — Factory information configuration registers Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id Reset 0xFFFFFFFF Id RW Field 1 Value Id AA A A A A A A AAAA A A A A A A A A A A A A A A A A A A A A 1 1 1 1 1 1 1 1111 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value Description DEVICEID[0] contains the least significant bits of the device identifier. DEVICEID[1] contains the most significant bits of the device identifier. 13.1.
13 FICR — Factory information configuration registers Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id Reset 0xFFFFFFFF Id RW Field A R 1 Value Id AA A A A A A A AAAA A A A A A A A A A A A A A A A A A A A A 1 1 1 1 1 1 1 1111 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value IR Description Identity Root, word n 13.1.
13 FICR — Factory information configuration registers Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id Reset 0xFFFFFFFF Id RW Field A R 1 Value Id AA A A A A A A AAAA A A A A A A A A A A A A A A A A A A A A 1 1 1 1 1 1 1 1111 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value Description DEVICEADDR 48 bit device address DEVICEADDR[0] contains the least significant bits of the device address.
13 FICR — Factory information configuration registers Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id Reset 0x00002000 Id RW Field A R 0 AA A A A A A A AAAA A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0000 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Description QF 0x2000 QFxx - 48-pin QFN CH 0x2001 CHxx - 7x8 WLCSP 56 balls CI 0x2002 CIxx - 7x8 WLCSP 56 balls Unspecified 0xFFFFFFFF Unspecified PACKAGE Pack
13 FICR — Factory information configuration registers Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id A A A A A A A A A A A A Reset 0x00000343 Id RW Field A R 0 Value Id 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 1 1 Value A Description A (slope definition) register. 13.1.23 TEMP.A2 Address offset: 0x40C Slope definition A2.
13 FICR — Factory information configuration registers Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id A A A A A A A A A A A A A A Reset 0x00003FCC Id RW Field A R 0 Value Id 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 0 0 Value B Description B (y-intercept) 13.1.28 TEMP.B1 Address offset: 0x420 y-intercept B1.
13 FICR — Factory information configuration registers Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id A A A A A A A A A A A A A A Reset 0x00003E10 Id RW Field A R 0 Value Id 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 0 0 0 0 Value B Description B (y-intercept) 13.1.33 TEMP.T0 Address offset: 0x434 Segment end T0.
13 FICR — Factory information configuration registers Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id A A A A A A A A Reset 0x00000050 Id RW Field A R 0 Value Id 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 Value T Description T (segment end)register. 13.1.38 NFC.TAGHEADER0 Address offset: 0x450 Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST.
13 FICR — Factory information configuration registers Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id Reset 0xFFFFFFFF 1 Value Id DD D D D D D D CCCC C C C C B B B B B B B B A A A A A A A A 1 1 1 1 1 1 1 1111 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Id RW Field Value Description A R UD12 Unique identifier byte 12 B R UD13 Unique identifier byte 13 C R UD14 Unique identifier byte 14 D R UD15 Unique identifier byte 15 Page 53
14 UICR — User information configuration registers 14 UICR — User information configuration registers The user information configuration registers (UICRs) are non-volatile memory (NVM) registers for configuring user specific settings. For information on writing UICR registers, see the NVMC — Non-volatile memory controller on page 29 and Memory on page 23 chapters. 14.
14 UICR — User information configuration registers Register Offset Description CUSTOMER[7] 0x09C Reserved for customer CUSTOMER[8] 0x0A0 Reserved for customer CUSTOMER[9] 0x0A4 Reserved for customer CUSTOMER[10] 0x0A8 Reserved for customer CUSTOMER[11] 0x0AC Reserved for customer CUSTOMER[12] 0x0B0 Reserved for customer CUSTOMER[13] 0x0B4 Reserved for customer CUSTOMER[14] 0x0B8 Reserved for customer CUSTOMER[15] 0x0BC Reserved for customer CUSTOMER[16] 0x0C0 Reserved for cu
14 UICR — User information configuration registers Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id Reset 0xFFFFFFFF Id RW Field A RW NRFFW 1 Value Id AA A A A A A A AAAA A A A A A A A A A A A A A A A A A A A A 1 1 1 1 1 1 1 1111 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value Description Reserved for Nordic firmware design 14.1.
14 UICR — User information configuration registers 14.1.9 NRFFW[8] Address offset: 0x034 Reserved for Nordic firmware design Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id Reset 0xFFFFFFFF Id RW Field A RW NRFFW 1 Value Id AA A A A A A A AAAA A A A A A A A A A A A A A A A A A A A A 1 1 1 1 1 1 1 1111 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value Description Reserved for Nordic firmware design 14.1.
14 UICR — User information configuration registers Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id Reset 0xFFFFFFFF Id RW Field A RW NRFFW 1 Value Id AA A A A A A A AAAA A A A A A A A A A A A A A A A A A A A A 1 1 1 1 1 1 1 1111 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value Description Reserved for Nordic firmware design 14.1.
14 UICR — User information configuration registers 14.1.20 NRFHW[4] Address offset: 0x060 Reserved for Nordic hardware design Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id Reset 0xFFFFFFFF Id RW Field A RW NRFHW 1 Value Id AA A A A A A A AAAA A A A A A A A A A A A A A A A A A A A A 1 1 1 1 1 1 1 1111 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value Description Reserved for Nordic hardware design 14.1.
14 UICR — User information configuration registers Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id Reset 0xFFFFFFFF Id RW Field A RW NRFHW 1 Value Id AA A A A A A A AAAA A A A A A A A A A A A A A A A A A A A A 1 1 1 1 1 1 1 1111 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value Description Reserved for Nordic hardware design 14.1.
14 UICR — User information configuration registers 14.1.31 CUSTOMER[3] Address offset: 0x08C Reserved for customer Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id Reset 0xFFFFFFFF Id RW Field A RW CUSTOMER 1 Value Id AA A A A A A A AAAA A A A A A A A A A A A A A A A A A A A A 1 1 1 1 1 1 1 1111 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value Description Reserved for customer 14.1.
14 UICR — User information configuration registers Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id Reset 0xFFFFFFFF Id RW Field A RW CUSTOMER 1 Value Id AA A A A A A A AAAA A A A A A A A A A A A A A A A A A A A A 1 1 1 1 1 1 1 1111 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value Description Reserved for customer 14.1.
14 UICR — User information configuration registers 14.1.42 CUSTOMER[14] Address offset: 0x0B8 Reserved for customer Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id Reset 0xFFFFFFFF Id RW Field A RW CUSTOMER 1 Value Id AA A A A A A A AAAA A A A A A A A A A A A A A A A A A A A A 1 1 1 1 1 1 1 1111 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value Description Reserved for customer 14.1.
14 UICR — User information configuration registers Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id Reset 0xFFFFFFFF Id RW Field A RW CUSTOMER 1 Value Id AA A A A A A A AAAA A A A A A A A A A A A A A A A A A A A A 1 1 1 1 1 1 1 1111 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value Description Reserved for customer 14.1.
14 UICR — User information configuration registers 14.1.53 CUSTOMER[25] Address offset: 0x0E4 Reserved for customer Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id Reset 0xFFFFFFFF Id RW Field A RW CUSTOMER 1 Value Id AA A A A A A A AAAA A A A A A A A A A A A A A A A A A A A A 1 1 1 1 1 1 1 1111 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value Description Reserved for customer 14.1.
14 UICR — User information configuration registers Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id Reset 0xFFFFFFFF Id RW Field A RW CUSTOMER AA A A A A A A AAAA A A A A A A A A A A A A A A A A A A A A 1 1 1 1 1 1 1 1111 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value Id Value Description Reserved for customer 14.1.
14 UICR — User information configuration registers Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id A A A A A A A A Reset 0xFFFFFFFF Id RW Field A RW PALL 1 Value Id 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value Description Enable or disable Access Port protection. Any other value than 0xFF being written to this field will enable protection. See Debug and trace on page 72 for more information.
15 Peripheral interface 15 Peripheral interface Peripherals are controlled by the CPU by writing to configuration registers and task registers. Peripheral events are indicated to the CPU by event registers and interrupts if they are configured for a given event. Task signal from PPI Peripheral TASK write k OR SHORTS task Peripheral core event INTEN m EVENT m IRQ signal to NVIC Event signal to PPI Figure 10: Tasks, events, shortcuts, and interrupts 15.
15 Peripheral interface • • • • Remove any PPI connections set up for the peripheral that is being disabled Clear all bits in the INTEN register, i.e. INTENCLR = 0xFFFFFFFF. Explicitly configure the peripheral that you enable and do not rely on configuration values that may be inherited from the peripheral that was disabled. Enable the now configured peripheral. For each of the rows in the following table, the instance ID listed is shared by the peripherals in the same row.
15 Peripheral interface 15.6 Events Events are used to notify peripherals and the CPU about events that have happened, for example, a state change in a peripheral. A peripheral may generate multiple events with each event having a separate register in that peripheral’s event register group. An event is generated when the peripheral itself toggles the corresponding event signal, and the event register is updated to reflect that the event has been generated.
15 Peripheral interface Page 71
16 Debug and trace 16 Debug and trace The debug and trace system offers a flexible and powerful mechanism for non-intrusive debugging. nRF52832 DAP SWDCLK External Debugger CTRL-AP NVMC SW-DP SWDIO APPROTECT.
16 Debug and trace 16.2 CTRL-AP - Control Access Port The Control Access Port (CTRL-AP) is a custom access port that enables control of the device even if the other access ports in the DAP are being disabled by the access port protection. Access port protection blocks the debugger from read and write access to all CPU registers and memorymapped addresses. See the UICR register APPROTECT on page 66 for more information about enabling access port protection.
16 Debug and trace Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id A Reset 0x00000000 Id RW Field A R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Description Ready 0 ERASEALL is ready Busy 1 ERASEALL is busy (on-going) ERASEALLSTATUS Status register for the ERASEALL operation APPROTECTSTATUS Address offset: 0x00C Status register for access port protection Bit number 31 30 29 28 27 26 25 24 23 22 21
16 Debug and trace Real-time debugging will allow interrupts to execute to completion in real time when breakpoints are set in Thread mode or lower priority interrupts. This enables the developer to set a breakpoint and singlestep through their code without a failure of the real-time event-driven threads running at higher priority.
17 Power and clock management 17 Power and clock management Power and clock management in nRF52832 is optimized for ultra-low power applications. The core of the power and clock management system is the Power Management Unit (PMU) illustrated in Figure 12: Power Management Unit on page 76.
17 Power and clock management Current consumption: Radio protocol configurations Symbol Description IS0 CPU running CoreMark from Flash, Radio 0 dBm TX @ 1 Mb/s Min. Typ. Max. Units 9.6 mA 9.0 mA Bluetooth Low Energy mode, Clock = HFXO, Cache enabled CPU running CoreMark from Flash, Radio RX @ 1 Mb/s IS1 Bluetooth Low Energy mode, Clock = HFXO, Cache enabled Current consumption: Ultra-low power Symbol Description ION_RAMOFF_EVENT System ON, No RAM retention, Wake on any event Min. 1.
18 POWER — Power supply 18 POWER — Power supply This device has the following power supply features: • • • • • • • On-chip LDO and DC/DC regulators Global System ON/OFF modes Individual RAM section power control for all system modes Analog or digital pin wakeup from System OFF Supervisor HW to manage power on reset, brownout, and power fail Auto-controlled refresh modes for LDO and DC/DC regulators to maximize efficiency Automatic switching between LDO and DC/DC regulator based on load to maximize efficie
18 POWER — Power supply POWER DCDCEN REG Supply LDO 1.3V System power VDD DC/DC DCC DEC4 GND Figure 14: DC/DC regulator setup 18.2 System OFF mode System OFF is the deepest power saving mode the system can enter. In this mode, the system’s core functionality is powered down and all ongoing tasks are terminated. The device can be put into System OFF mode using the POWER register interface. When in System OFF mode, the device can be woken up through one of the following signals: 1. 2. 3. 4.
18 POWER — Power supply 18.3 System ON mode System ON is the default state after power-on reset. In System ON, all functional blocks such as the CPU or peripherals, can be in IDLE or RUN mode, depending on the configuration set by the software and the state of the application executing. Register RESETREAS on page 85 provides information about the source that caused the wakeup or reset.
18 POWER — Power supply VDD C Power on reset R V BOR POFCON Brownout reset 1.7V ........... MUX P OFWARN Vpof 2.8V Figure 15: Power supply supervisor 18.4.1 Power-fail comparator The power-fail comparator (POF) can provide the CPU with an early warning of impending power failure. It will not reset the system, but give the CPU time to prepare for an orderly power-down.
18 POWER — Power supply 18.5 RAM sections RAM section power control is used for retention in System OFF mode and for powering down unused sections in System ON mode. Each RAM section can power up and down independently in both System ON and System OFF mode. See chapter Memory on page 23 for more information on RAM sections. 18.6 Reset There are multiple sources that may trigger a reset. After a reset has occurred, register RESETREAS can be read to determine which source generated the reset. 18.6.
18 POWER — Power supply 18.7 Retained registers A retained register is a register that will retain its value in System OFF mode and through a reset, depending on reset source. See individual peripheral chapters for information of which registers are retained for the various peripherals. 18.
18 POWER — Power supply Register Offset Description RAM[0].POWERSET 0x904 RAM0 power control set register RAM[0].POWERCLR 0x908 RAM0 power control clear register RAM[1].POWER 0x910 RAM1 power control register RAM[1].POWERSET 0x914 RAM1 power control set register RAM[1].POWERCLR 0x918 RAM1 power control clear register RAM[2].POWER 0x920 RAM2 power control register RAM[2].POWERSET 0x924 RAM2 power control set register RAM[2].POWERCLR 0x928 RAM2 power control clear register RAM[3].
18 POWER — Power supply Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id C B Reset 0x00000000 Id RW Field A RW POFWARN 0 Value Id A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Description Write '1' to Disable interrupt for POFWARN event See EVENTS_POFWARN B Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW SLEEPENTER Write '1' to Disable interrupt for SLEEPENTER event See EVENTS_SLEEPENTER
18 POWER — Power supply Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 Id HG F E Reset 0x00000000 Id RW Field H RW NFC 0 Value Id 0 0 0 0 0 0 0 000000000000000000 Value 5 4 3 2 1 0 D C B A 0 0 0 0 0 0 Description Reset due to wake up from System OFF mode by NFC field detect NotDetected 0 Not detected Detected 1 Detected 18.9.
18 POWER — Power supply Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id B B B B A Reset 0x00000000 Id RW Field B RW THRESHOLD 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Description Enabled 1 Enable V17 4 Set threshold to 1.7 V V18 5 Set threshold to 1.8 V V19 6 Set threshold to 1.9 V V20 7 Set threshold to 2.0 V V21 8 Set threshold to 2.1 V V22 9 Set threshold to 2.
18 POWER — Power supply Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id D C Reset 0x00000003 Id RW Field B RW ONRAM1 C D 0 B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 Value Id Value Description RAM0On 1 On RAM1Off 0 Off RAM1On 1 On RAM0Off 0 Off RAM0On 1 On RAM1Off 0 Off RAM1On 1 On Keep RAM block 1 on or off in system ON Mode RW OFFRAM0 Keep retention on RAM block 0 when RAM block is switched o
18 POWER — Power supply Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id D C Reset 0x0000FFFF Id RW Field A RW S0POWER 0 Value Id B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value Description Keep RAM section S0 ON or OFF in System ON mode. RAM sections are always retained when ON, but can also be retained when OFF dependent on the settings in S0RETENTION. All RAM sections will be OFF in System OFF mode.
18 POWER — Power supply Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id D C Reset 0x0000FFFF Id C RW Field W 0 B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value Id Value Description Off 1 Off S0RETENTION Keep retention on RAM section S0 when RAM section is switched off Off D W 1 Off S1RETENTION Keep retention on RAM section S1 when RAM section is switched off Off 1 Off 18.9.15 RAM[1].
18 POWER — Power supply Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 Id 6 5 4 3 2 1 0 DC Reset 0x0000FFFF Id RW Field D W 0 Value Id 0 0 0 0 0 0 0 00000000111111111 Value B A 1 1 1 1 1 1 1 Description S1RETENTION Keep retention on RAM section S1 when RAM section is switched off On 1 On 18.9.17 RAM[1].POWERCLR Address offset: 0x918 RAM1 power control clear register When read, this register will return the value of the POWER register.
18 POWER — Power supply 18.9.19 RAM[2].POWERSET Address offset: 0x924 RAM2 power control set register When read, this register will return the value of the POWER register.
18 POWER — Power supply Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 Id DC Reset 0x0000FFFF Id RW Field 0 Value Id 000000000000000111111111111 Value 3 2 1 0 B A 1 1 1 1 Description RAM sections are always retained when ON, but can also be retained when OFF dependent on the settings in S1RETENTION. All RAM sections will be OFF in System OFF mode.
18 POWER — Power supply 18.9.24 RAM[4].POWER Address offset: 0x940 RAM4 power control register Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id D C Reset 0x0000FFFF Id RW Field A RW S0POWER 0 Value Id B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value Description Keep RAM section S0 ON or OFF in System ON mode.
18 POWER — Power supply Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id D C Reset 0x0000FFFF Id RW Field A W B C W W 0 B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value Id Value Off 1 Off 1 Description S0POWER Keep RAM section S0 of RAM4 on or off in System ON mode Off S1POWER Keep RAM section S1 of RAM4 on or off in System ON mode Off S0RETENTION Keep retention on RAM section S0 when RAM section is switched
18 POWER — Power supply Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id D C Reset 0x0000FFFF Id RW Field C W 0 Value Id B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value Description S0RETENTION Keep retention on RAM section S0 when RAM section is switched off On D W 1 On S1RETENTION Keep retention on RAM section S1 when RAM section is switched off On 1 On 18.9.29 RAM[5].
18 POWER — Power supply Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id D C Reset 0x0000FFFF Id RW Field 0 B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value Id Value Description On 1 On 18.9.31 RAM[6].POWERSET Address offset: 0x964 RAM6 power control set register When read, this register will return the value of the POWER register.
18 POWER — Power supply Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id D C Reset 0x0000FFFF Id RW Field 0 Value Id B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value Description RAM sections are always retained when ON, but can also be retained when OFF dependent on the settings in S0RETENTION. All RAM sections will be OFF in System OFF mode.
18 POWER — Power supply Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id D C Reset 0x0000FFFF Id RW Field C W 0 Value Id B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value Description S0RETENTION Keep retention on RAM section S0 when RAM section is switched off Off D W 1 Off S1RETENTION Keep retention on RAM section S1 when RAM section is switched off Off 1 Off 18.10 Electrical specification 18.10.
18 POWER — Power supply Symbol Description VPOFHYST Threshold voltage hysteresis Min. Typ. Max. VBOR,OFF Brown out reset voltage range SYSTEM OFF mode 1.2 1.7 V VBOR,ON Brown out reset voltage range SYSTEM ON mode 1.5 1.
19 CLOCK — Clock control 19 CLOCK — Clock control The clock control system can source the system clocks from a range of internal or external high and low frequency oscillators and distribute them to modules based upon a module’s individual requirements. Clock distribution is automated and grouped independently by module to limit current consumption in unused branches of the clock tree.
19 CLOCK — Clock control When the system requests one or more clocks from the HFCLK controller, the HFCLK controller will automatically provide them. If the system does not request any clocks provided by the HFCLK controller, the controller will enter a power saving mode. These clocks are only available when the system is in ON mode. When the system enters ON mode, the internal oscillator (HFINT) clock source will automatically start to be able to provide the required HFCLK clock(s) for the system.
19 CLOCK — Clock control 19.2 LFCLK clock controller The system supports several low frequency clock sources. As illustrated in Figure 17: Clock control on page 101, the system supports the following low frequency clock sources: • • • 32.768 kHz RC oscillator (LFRC) 32.768 kHz crystal oscillator (LFXO) 32.768 kHz synthesized from HFCLK (LFSYNT) The LFCLK clock is started by first selecting the preferred clock source in register LFCLKSRC on page 108 and then triggering the LFCLKSTART task.
19 CLOCK — Clock control 19.2.4 32.768 kHz crystal oscillator (LFXO) For higher LFCLK accuracy (when better than +/- 250 ppm accuracy is required), the low frequency crystal oscillator (LFXO) must be used. The following external clock sources are supported: • • Low swing clock signal applied to the XL1 pin. The XL2 pin shall then be grounded. Rail-to-rail clock signal applied to the XL1 pin. The XL2 pin shall then be grounded or left unconnected.
19 CLOCK — Clock control 19.2.5 32.768 kHz synthesized from HFCLK (LFSYNT) LFCLK can also be synthesized from the HFCLK clock source. The accuracy of LFCLK will then be the accuracy of the HFCLK. Using the LFSYNT clock avoids the requirement for a 32.768 kHz crystal, but increases average power consumption as the HFCLK will need to be requested in the system. 19.
19 CLOCK — Clock control Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id D C Reset 0x00000000 Id RW Field C RW DONE 0 Value Id B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Description Write '1' to Enable interrupt for DONE event See EVENTS_DONE D Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW CTTO Write '1' to Enable interrupt for CTTO event See EVENTS_CTTO Set 1 Enable Disabled 0
19 CLOCK — Clock control 19.3.
19 CLOCK — Clock control 19.3.8 LFCLKSRC Address offset: 0x518 Clock source for the LFCLK Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id C B Reset 0x00000000 Id RW Field A RW SRC B 0 A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Description RC 0 32.768 kHz RC oscillator Xtal 1 32.768 kHz crystal oscillator Synth 2 32.
19 CLOCK — Clock control 19.4 Electrical specification 19.4.1 64 MHz internal oscillator (HFINT) Symbol Description fNOM_HFINT Nominal output frequency Min. Typ. 64 Max. Units fTOL_HFINT Frequency tolerance <±1.5 IHFINT Run current 60 µA ISTART_HFINT Average startup current I_HFINT µA tSTART_HFINT Startup time 3 us MHz <±6 % 19.4.2 64 MHz crystal oscillator (HFXO) Symbol Description fNOM_HFXO Nominal output frequency Min. Typ.
19 CLOCK — Clock control Symbol Description tSTART_LFXO Startup time for 32.768 kHz crystal oscillator Min. VAMP_IN_XO_LOW Peak to peak amplitude for external low swing clock. Input Typ. Max. Units 1000 mV Max. Units 0.25 200 s signal must not swing outside supply rails. 19.4.5 32.768 kHz synthesized from HFCLK (LFSYNT) Symbol Description fNOM_LFSYNT Nominal frequency Min. Typ. 32.
20 GPIO — General purpose input/output 20 GPIO — General purpose input/output The general purpose input/output (GPIO) is organized as one port with up to 32 I/Os (dependent on package) enabling access and control of up to 32 pins through one port. Each GPIO can be accessed individually.
20 GPIO — General purpose input/output LDETECT PIN0 ANAEN DETECTMODE DETECT GPIO Port DIR_OVERRIDE PIN[0].CNF.DRIVE OUT_OVERRIDE PIN0 OUT LATCH PIN[0].IN PIN[0].CNF.DIR PIN0.DETECT PIN0 PIN[0].OUT O PIN[0].OUT PIN[0].CNF Sense PIN1.DETECT PIN[0].CNF.SENSE .. PIN[0].CNF.PULL PIN[0].CNF.INPUT PIN31.DETECT PIN[0].IN I PIN31 IN PIN31 PIN[31].OUT PIN[31].IN PIN[31].
20 GPIO — General purpose input/output PIN31.DETECT PIN1.DETECT PIN0.DETECT DETECT (Default mode) LATCH.31 LATCH.1 LATCH.0 3 4 LATCH = (1 << 31) LATCH = (1<<1) 2 LATCH = (1<<0) 1 LATCH = (1<<1) CPU DETECT (LDETECT mode) Figure 22: DETECT signal behavior The input buffer of a GPIO pin can be disconnected from the pin to enable power savings when the pin is not used as an input, see Figure 21: GPIO Port and the GPIO pin details on page 112.
20 GPIO — General purpose input/output Table 29: Register Overview Register Offset Description OUT 0x504 Write GPIO port OUTSET 0x508 Set individual bits in GPIO port OUTCLR 0x50C Clear individual bits in GPIO port IN 0x510 Read GPIO port DIR 0x514 Direction of GPIO pins DIRSET 0x518 DIR set register DIRCLR 0x51C DIR clear register LATCH 0x520 Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].
20 GPIO — General purpose input/output Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id f e d c b a Z Y X W VUT S R Q P O N M L K J Reset 0x00000000 0 0 0 0 0 0 0 0 000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Id C D E F G H I J K L M N O P Q R S T RW Field Value Id Value Description Low 0 Pin driver is low High 1 Pin driver is high Low 0 Pin driver is low High 1 Pin driver is high Low 0 Pin driver is low High
20 GPIO — General purpose input/output Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id f e d c b a Z Y X W VUT S R Q P O N M L K J Reset 0x00000000 0 0 0 0 0 0 0 0 000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Id U V W X Y Z a b c d e f RW Field Value Id Value Description High 1 Pin driver is high Low 0 Pin driver is low High 1 Pin driver is high Low 0 Pin driver is low High 1 Pin driver is high Low 0 Pin driver is
20 GPIO — General purpose input/output Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id f e d c b a Z Y X W V U T S R Q P O N M L K J E D C B A Reset 0x00000000 0 0 0 0 0 0 0 0 0000000000000000000 Id C D E F G H I J K L M N O P RW Field I HGF Value Id Value Description High 1 Read: pin driver is high Set 1 Write: writing a '1' sets the pin high; writing a '0' has no effect Low 0 Read: pin driver is low High 1 Read:
20 GPIO — General purpose input/output Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id f e d c b a Z Y X W V U T S R Q P O N M L K J E D C B A Reset 0x00000000 0 0 0 0 0 0 0 0 0000000000000000000 Id Q R S T U V W X Y Z a b c RW Field I HGF Value Id Value Description Low 0 Read: pin driver is low High 1 Read: pin driver is high Set 1 Write: writing a '1' sets the pin high; writing a '0' has no effect Low 0 Read: pin
20 GPIO — General purpose input/output Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id f e d c b a Z Y X W V U T S R Q P O N M L K J E D C B A Reset 0x00000000 0 0 0 0 0 0 0 0 0000000000000000000 Id RW Field d RW PIN29 e f I HGF 0 0 0 0 0 Value Id Value Description Low 0 Read: pin driver is low High 1 Read: pin driver is high Set 1 Write: writing a '1' sets the pin high; writing a '0' has no effect Low 0 Read: pin driver is
20 GPIO — General purpose input/output Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id f e d c b a Z Y X W V U T S R Q P O N M L K J Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Id I J K L M N O P Q R S T U V RW Field I H G F E D C B A Value Id Value Description Clear 1 Write: writing a '1' sets the pin low; writing a '0' has no effect Low 0 Read: pin driver is low High 1 Read: pin dri
20 GPIO — General purpose input/output Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id f e d c b a Z Y X W V U T S R Q P O N M L K J E D C B A Reset 0x00000000 0 0 0 0 0 0 0 0 0000000000000000000 Id W X Y Z a b c d e f RW Field I HGF 0 0 0 0 0 Value Id Value Description High 1 Read: pin driver is high Clear 1 Write: writing a '1' sets the pin low; writing a '0' has no effect Low 0 Read: pin driver is low High 1 Read:
20 GPIO — General purpose input/output Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id f e d c b a Z Y X W VUT S R Q P O N M L K J Reset 0x00000000 0 0 0 0 0 0 0 0 00000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Id RW Field B R C D E F G H I J K L M N O P Q R S T R R R R R R R R R R R R R R R R R R Value Id Value Description Low 0 Pin input is low High 1 Pin input is high Low 0 Pin input is low Hig
20 GPIO — General purpose input/output Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id f e d c b a Z Y X W VUT S R Q P O N M L K J Reset 0x00000000 0 0 0 0 0 0 0 0 00000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Id U V W X Y Z a b c d e f RW Field R R R R R R R R R R R R Value Id Value Description Low 0 Pin input is low High 1 Pin input is high Low 0 Pin input is low High 1 Pin input is high Low 0 Pin input
20 GPIO — General purpose input/output Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id f e d c b a Z Y XWVU T S R Q P O N M L K J Reset 0x00000000 0 0 0 0 0 0 0 0 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Id D E F G H I J K L M N O P Q R S T U RW Field Value Id Value Description Input 0 Pin set as input Output 1 Pin set as output Input 0 Pin set as input Output 1 Pin set as output Input 0 Pin set as inpu
20 GPIO — General purpose input/output Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id f e d c b a Z Y XWVU T S R Q P O N M L K J Reset 0x00000000 0 0 0 0 0 0 0 0 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Id RW Field V RW PIN21 W X Y Z a b c d e f Value Id Value Description Output 1 Pin set as output Input 0 Pin set as input Output 1 Pin set as output Input 0 Pin set as input Output 1 Pin set as output Input
20 GPIO — General purpose input/output Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id f e d c b a Z Y XWVU T S R Q P O N M L K J Reset 0x00000000 0 0 0 0 0 0 0 0 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Id D E F G H I J K L M N O P RW Field I H G F E D C B A Value Id Value Description Input 0 Read: pin set as input Output 1 Read: pin set as output Set 1 Write: writing a '1' sets pin to output; writing a '0' has
20 GPIO — General purpose input/output Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id f e d c b a Z Y XWVU T S R Q P O N M L K J Reset 0x00000000 0 0 0 0 0 0 0 0 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Id RW Field Q RW PIN16 R S T U V W X Y Z a b c d I H G F E D C B A Value Id Value Description Input 0 Read: pin set as input Output 1 Read: pin set as output Set 1 Write: writing a '1' sets pin to output; writi
20 GPIO — General purpose input/output Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id f e d c b a Z Y X W V U T S R Q P O N M L K J Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 Id e f RW Field I H G F ED C B A Value Id Value Set 1 Description Input 0 Read: pin set as input Output 1 Read: pin set as output Set 1 Write: writing a '1' sets pin to output; writing a '0' has no effect Input 0 Read:
20 GPIO — General purpose input/output Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id f e d c b a Z Y XWVU T S R Q P O N M L K J Reset 0x00000000 0 0 0 0 0 0 0 0 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Id J K L M N O P Q R S T U V W RW Field I H G F E D C B A Value Id Value Description Output 1 Read: pin set as output Clear 1 Write: writing a '1' sets pin to input; writing a '0' has no effect Input 0 Read: pin
20 GPIO — General purpose input/output Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id f e d c b a Z Y XWVU T S R Q P O N M L K J Reset 0x00000000 0 0 0 0 0 0 0 0 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Id X Y Z a b c d e f RW Field I H G F E D C B A Value Id Value Description Input 0 Read: pin set as input Output 1 Read: pin set as output Clear 1 Write: writing a '1' sets pin to input; writing a '0' has no effect
20 GPIO — General purpose input/output Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id f e d c b a Z Y X W VUT S RQ P O N M L K J Reset 0x00000000 0 0 0 0 0 0 0 0 00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Id C RW Field Value Id Value Description NotLatched 0 Criteria has not been met Latched 1 Criteria has been met RW PIN2 I H G F E D C B A Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear.
20 GPIO — General purpose input/output Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Id f e d c b a Z Y X W VU T S RQPO N ML KJ I H G F E D C B A Reset 0x00000000 0 0 0 0 0 0 0 0 000000000000000 0 0 0 0 0 0 0 0 0 Id RW Field P RW PIN15 Value Id Value Description Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear.
20 GPIO — General purpose input/output Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id f e d c b a Z Y XWVU T S R Q P O N M L K J Reset 0x00000000 0 0 0 0 0 0 0 0 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Id RW Field d RW PIN29 Value Id Value Description Latched 1 Criteria has been met I H G F E D C B A Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear.
20 GPIO — General purpose input/output Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 Id E E Reset 0x00000002 Id RW Field 0 DDD 0 0 0 0 0 0 0 000000000000000000 5 4 3 2 1 0 C C B A 0 0 0 0 1 0 Value Id Value Description D0H1 5 Disconnect '0', high drive '1' (normally used for wired-or S0D1 6 H0D1 7 connections) Standard '0'.
20 GPIO — General purpose input/output Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id E E Reset 0x00000002 Id RW Field A RW DIR B C D 0 D D D C C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Value Id Value Description Input 0 Configure pin as an input pin Output 1 Configure pin as an output pin Connect 0 Connect input buffer Disconnect 1 Disconnect input buffer Disabled 0 No pull Pulldown 1 Pull dow
20 GPIO — General purpose input/output Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 Id E E Reset 0x00000002 Id RW Field 0 DDD 0 0 0 0 0 0 0 000000000000000000 5 4 3 2 1 0 C C B A 0 0 0 0 1 0 Value Id Value Description D0H1 5 Disconnect '0', high drive '1' (normally used for wired-or S0D1 6 H0D1 7 connections) Standard '0'.
20 GPIO — General purpose input/output Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id E E Reset 0x00000002 Id RW Field A RW DIR B C D 0 D D D C C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Value Id Value Description Input 0 Configure pin as an input pin Output 1 Configure pin as an output pin Connect 0 Connect input buffer Disconnect 1 Disconnect input buffer Disabled 0 No pull Pulldown 1 Pull dow
20 GPIO — General purpose input/output Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 Id E E Reset 0x00000002 Id RW Field 0 DDD 0 0 0 0 0 0 0 000000000000000000 5 4 3 2 1 0 C C B A 0 0 0 0 1 0 Value Id Value Description D0H1 5 Disconnect '0', high drive '1' (normally used for wired-or S0D1 6 H0D1 7 connections) Standard '0'.
20 GPIO — General purpose input/output Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id E E Reset 0x00000002 Id RW Field A RW DIR B C D 0 D D D C C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Value Id Value Description Input 0 Configure pin as an input pin Output 1 Configure pin as an output pin Connect 0 Connect input buffer Disconnect 1 Disconnect input buffer Disabled 0 No pull Pulldown 1 Pull dow
20 GPIO — General purpose input/output Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 Id E E Reset 0x00000002 Id RW Field 0 DDD 0 0 0 0 0 0 0 000000000000000000 5 4 3 2 1 0 C C B A 0 0 0 0 1 0 Value Id Value Description D0H1 5 Disconnect '0', high drive '1' (normally used for wired-or S0D1 6 H0D1 7 connections) Standard '0'.
20 GPIO — General purpose input/output Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id E E Reset 0x00000002 Id RW Field A RW DIR B C D 0 D D D C C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Value Id Value Description Input 0 Configure pin as an input pin Output 1 Configure pin as an output pin Connect 0 Connect input buffer Disconnect 1 Disconnect input buffer Disabled 0 No pull Pulldown 1 Pull dow
20 GPIO — General purpose input/output Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 Id E E Reset 0x00000002 Id RW Field 0 DDD 0 0 0 0 0 0 0 000000000000000000 5 4 3 2 1 0 C C B A 0 0 0 0 1 0 Value Id Value Description D0H1 5 Disconnect '0', high drive '1' (normally used for wired-or S0D1 6 H0D1 7 connections) Standard '0'.
20 GPIO — General purpose input/output Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id E E Reset 0x00000002 Id RW Field A RW DIR B C D 0 D D D C C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Value Id Value Description Input 0 Configure pin as an input pin Output 1 Configure pin as an output pin Connect 0 Connect input buffer Disconnect 1 Disconnect input buffer Disabled 0 No pull Pulldown 1 Pull dow
20 GPIO — General purpose input/output Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 Id E E Reset 0x00000002 Id RW Field 0 DDD 0 0 0 0 0 0 0 000000000000000000 5 4 3 2 1 0 C C B A 0 0 0 0 1 0 Value Id Value Description D0H1 5 Disconnect '0', high drive '1' (normally used for wired-or S0D1 6 H0D1 7 connections) Standard '0'.
20 GPIO — General purpose input/output Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id E E Reset 0x00000002 Id RW Field A RW DIR B C D 0 D D D C C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Value Id Value Description Input 0 Configure pin as an input pin Output 1 Configure pin as an output pin Connect 0 Connect input buffer Disconnect 1 Disconnect input buffer Disabled 0 No pull Pulldown 1 Pull dow
20 GPIO — General purpose input/output Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 Id E E Reset 0x00000002 Id RW Field 0 DDD 0 0 0 0 0 0 0 000000000000000000 5 4 3 2 1 0 C C B A 0 0 0 0 1 0 Value Id Value Description D0H1 5 Disconnect '0', high drive '1' (normally used for wired-or S0D1 6 H0D1 7 connections) Standard '0'.
20 GPIO — General purpose input/output Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id E E Reset 0x00000002 Id RW Field A RW DIR B C D 0 D D D C C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Value Id Value Description Input 0 Configure pin as an input pin Output 1 Configure pin as an output pin Connect 0 Connect input buffer Disconnect 1 Disconnect input buffer Disabled 0 No pull Pulldown 1 Pull dow
20 GPIO — General purpose input/output Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 Id E E Reset 0x00000002 Id RW Field 0 DDD 0 0 0 0 0 0 0 000000000000000000 5 4 3 2 1 0 C C B A 0 0 0 0 1 0 Value Id Value Description D0H1 5 Disconnect '0', high drive '1' (normally used for wired-or S0D1 6 H0D1 7 connections) Standard '0'.
20 GPIO — General purpose input/output Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id E E Reset 0x00000002 Id RW Field A RW DIR B C D 0 D D D C C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Value Id Value Description Input 0 Configure pin as an input pin Output 1 Configure pin as an output pin Connect 0 Connect input buffer Disconnect 1 Disconnect input buffer Disabled 0 No pull Pulldown 1 Pull dow
20 GPIO — General purpose input/output Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 Id E E Reset 0x00000002 Id RW Field 0 DDD 0 0 0 0 0 0 0 000000000000000000 5 4 3 2 1 0 C C B A 0 0 0 0 1 0 Value Id Value Description D0H1 5 Disconnect '0', high drive '1' (normally used for wired-or S0D1 6 H0D1 7 connections) Standard '0'.
20 GPIO — General purpose input/output Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id E E Reset 0x00000002 Id RW Field A RW DIR B C D 0 D D D C C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Value Id Value Description Input 0 Configure pin as an input pin Output 1 Configure pin as an output pin Connect 0 Connect input buffer Disconnect 1 Disconnect input buffer Disabled 0 No pull Pulldown 1 Pull dow
20 GPIO — General purpose input/output Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 Id E E Reset 0x00000002 Id RW Field 0 DDD 0 0 0 0 0 0 0 000000000000000000 5 4 3 2 1 0 C C B A 0 0 0 0 1 0 Value Id Value Description D0H1 5 Disconnect '0', high drive '1' (normally used for wired-or S0D1 6 H0D1 7 connections) Standard '0'.
20 GPIO — General purpose input/output Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id E E Reset 0x00000002 Id RW Field A RW DIR B C D 0 D D D C C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Value Id Value Description Input 0 Configure pin as an input pin Output 1 Configure pin as an output pin Connect 0 Connect input buffer Disconnect 1 Disconnect input buffer Disabled 0 No pull Pulldown 1 Pull dow
20 GPIO — General purpose input/output Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 Id E E Reset 0x00000002 Id 0 RW Field 5 4 3 2 1 0 DDD C C B A 0 0 0 0 0 0 0 000000000000000000 0 0 0 0 1 0 Value Id Value Description D0H1 5 Disconnect '0', high drive '1' (normally used for wired-or S0D1 6 H0D1 7 connections) Standard '0'.
20 GPIO — General purpose input/output Symbol Description Min. VIL Input low voltage VSS Typ. Max. 0.3 x VDD V VOH,SD Output high voltage, standard drive, 0.5 mA, VDD ≥1.7 VDD-0.4 VDD V VOH,HDH Output high voltage, high drive, 5 mA, VDD >= 2.7 V VDD-0.4 VDD V VOH,HDL Output high voltage, high drive, 3 mA, VDD >= 1.7 V VDD-0.4 VDD V VOL,SD Output low voltage, standard drive, 0.5 mA, VDD ≥1.7 VSS VSS+0.4 V VOL,HDH Output low voltage, high drive, 5 mA, VDD >= 2.7 V VSS VSS+0.
20 GPIO — General purpose input/output 30.00 Pad current [mA] 25.00 20.00 15.00 10.00 5.00 0.00 0 0.5 1 1.5 2 2.5 3 3.5 Pad voltage [V] Figure 24: GPIO drive strength vs Voltage, high drive, VDD = 3.0 V 9.00 8.00 Pad current [mA] 7.00 6.00 5.00 4.00 3.00 2.00 1.00 0.00 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 2.8 3 3.2 3.4 3.6 55 65 75 VDD [V] Figure 25: Max sink current vs Voltage, standard drive 35.00 30.00 Pad current [mA] 25.00 20.00 15.00 10.00 5.00 0.00 1.6 1.
21 GPIOTE — GPIO tasks and events 21 GPIOTE — GPIO tasks and events The GPIO tasks and events (GPIOTE) module provides functionality for accessing GPIO pins using tasks and events. Each GPIOTE channel can be assigned to one pin. A GPIOTE block enables GPIOs to generate events on pin state change which can be used to carry out tasks through the PPI system. A GPIO can also be driven to change state on system events using the PPI system.
21 GPIOTE — GPIO tasks and events When setting the CONFIG[n] registers, MODE=Disabled does not have the same effect as MODE=Task and POLARITY=None. In the latter case, a CLR or SET task occurring at the exact same time as OUT will end up with no change on the pin, according to the priorities described in the table above. When a GPIOTE channel is configured to operate on a pin as a task, the initial value of that pin is configured in the OUTINIT field of CONFIG[n]. 21.
21 GPIOTE — GPIO tasks and events Register Offset Description TASKS_OUT[2] 0x008 Task for writing to pin specified in CONFIG[2].PSEL. Action on pin is configured in TASKS_OUT[3] 0x00C TASKS_OUT[4] 0x010 TASKS_OUT[5] 0x014 TASKS_OUT[6] 0x018 TASKS_OUT[7] 0x01C TASKS_SET[0] 0x030 Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is to set it high. TASKS_SET[1] 0x034 Task for writing to pin specified in CONFIG[1].PSEL. Action on pin is to set it high.
21 GPIOTE — GPIO tasks and events Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id I H G F E D C B A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Id RW Field Value Id Value Description Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled See EVENTS_IN[0] B RW IN1 Write '1' to Enable interrupt for IN[1] event See EVENTS_IN[1] C Set 1 Enable Disabled 0 Read: Disabled Enabled 1 R
21 GPIOTE — GPIO tasks and events Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id I H G F E D C B A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Id RW Field A RW IN0 Value Id Value Description Write '1' to Disable interrupt for IN[0] event See EVENTS_IN[0] B Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW IN1 Write '1' to Disable interrupt for IN[1] event See EVENTS_IN[1]
21 GPIOTE — GPIO tasks and events Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id D Reset 0x00000000 Id RW Field A RW MODE 0 C C B B B B B A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Disabled 0 Event 1 Description Mode Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module.
21 GPIOTE — GPIO tasks and events Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 Id D Reset 0x00000000 Id RW Field B RW PSEL 0 Value Id C C 4 3 2 1 0 BBBBB A A 00000000000000000000000000 0 0 0 0 0 Value Description [0..31] GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event C RW POLARITY When In task mode: Operation to be performed on output when OUT[n] task is triggered.
21 GPIOTE — GPIO tasks and events Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 Id D Reset 0x00000000 Id RW Field D RW OUTINIT 0 Value Id C C BBBBB A A 000000000000000000000000000 Value 3 2 1 0 0 0 0 0 Description When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect.
21 GPIOTE — GPIO tasks and events Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id D Reset 0x00000000 Id RW Field A RW MODE 0 C C B B B B B A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Disabled 0 Event 1 Description Mode Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module.
21 GPIOTE — GPIO tasks and events Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 Id D Reset 0x00000000 Id RW Field B RW PSEL 0 Value Id C C 4 3 2 1 0 BBBBB A A 00000000000000000000000000 0 0 0 0 0 Value Description [0..31] GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event C RW POLARITY When In task mode: Operation to be performed on output when OUT[n] task is triggered.
21 GPIOTE — GPIO tasks and events Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 Id D Reset 0x00000000 Id RW Field D RW OUTINIT 0 Value Id C C A A 000000000000000000000000000 Value 3 2 1 0 BBBBB 0 0 0 0 Description When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect.
22 PPI — Programmable peripheral interconnect 22 PPI — Programmable peripheral interconnect The Programmable peripheral interconnect (PPI) enables peripherals to interact autonomously with each other using tasks and events independent of the CPU. The PPI allows precise synchronization between peripherals when real-time application constraints exist and eliminates the need for CPU activity to implement behavior which can be predefined using PPI. CH[1].EEP CH[0].EEP Peripheral 1 Peripheral 2 CH[n].
22 PPI — Programmable peripheral interconnect Note that shortcuts (as defined in the SHORTS register in each peripheral) are not affected by this 16 MHz synchronization, and are therefore not delayed. Each TEP implements a fork mechanism that enables a second task to be triggered at the same time as the task specified in the TEP is triggered. This second task is configured in the task end point register in the FORK registers groups, e.g. FORK.TEP[0] is associated with PPI channel CH[0].
22 PPI — Programmable peripheral interconnect Register Offset Description TASKS_CHG[4].DIS 0x024 Disable channel group 4 TASKS_CHG[5].EN 0x028 Enable channel group 5 TASKS_CHG[5].DIS 0x02C Disable channel group 5 CHEN 0x500 Channel enable register CHENSET 0x504 Channel enable set register CHENCLR 0x508 Channel enable clear register CH[0].EEP 0x510 Channel 0 event end-point CH[0].TEP 0x514 Channel 0 task end-point CH[1].EEP 0x518 Channel 1 event end-point CH[1].
22 PPI — Programmable peripheral interconnect Register Offset Description FORK[6].TEP 0x928 Channel 6 task end-point FORK[7].TEP 0x92C Channel 7 task end-point FORK[8].TEP 0x930 Channel 8 task end-point FORK[9].TEP 0x934 Channel 9 task end-point FORK[10].TEP 0x938 Channel 10 task end-point FORK[11].TEP 0x93C Channel 11 task end-point FORK[12].TEP 0x940 Channel 12 task end-point FORK[13].TEP 0x944 Channel 13 task end-point FORK[14].TEP 0x948 Channel 14 task end-point FORK[15].
22 PPI — Programmable peripheral interconnect Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id f e d c b a Z Y X W VUT S R Q P O N M L K J Reset 0x00000000 0 0 0 0 0 0 0 0 00000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Id I J K L M N O P Q R S T U V W X Y Z RW Field Value Id Value Description Disabled 0 Disable channel Enabled 1 Enable channel Disabled 0 Disable channel Enabled 1 Enable channel Disabled 0 Disable
22 PPI — Programmable peripheral interconnect Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id f e d c b a Z Y X W VUT S R Q P O N M L K J Reset 0x00000000 0 0 0 0 0 0 0 0 00000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Id a b c d e f RW Field Value Id Value Description Enabled 1 Enable channel Disabled 0 Disable channel Enabled 1 Enable channel Disabled 0 Disable channel Enabled 1 Enable channel Disabled 0 Disable channel
22 PPI — Programmable peripheral interconnect Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id f e d c b a Z Y XWVU T S R Q P O N M L K J Reset 0x00000000 0 0 0 0 0 0 0 0 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Id RW Field G RW CH6 H I J K L M N O P Q R S T Value Id Value Disabled 0 Read: channel disabled Enabled 1 Read: channel enabled Set 1 Write: Enable channel Disabled 0 Read: channel disabled Enabled 1
22 PPI — Programmable peripheral interconnect Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id f e d c b a Z Y X W VUT S R Q P O N M L K J Reset 0x00000000 0 0 0 0 0 0 0 0 0000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Id U V W X Y Z a b c d e f RW Field Value Id Value Description Set 1 Write: Enable channel Disabled 0 Read: channel disabled Enabled 1 Read: channel enabled Set 1 Write: Enable channel Disabled 0 Read: chan
22 PPI — Programmable peripheral interconnect Read: reads value of CH{i} field in CHEN register. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id f e d c b a Z Y XWVU T S R Q P O N M L K J Reset 0x00000000 0 0 0 0 0 0 0 0 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Id RW Field A RW CH0 B C D E F G H I J K L M N Value Id Value I H G F E D C B A Description Channel 0 enable clear register.
22 PPI — Programmable peripheral interconnect Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id f e d c b a Z Y X W VUT S RQ P O N M L K J Reset 0x00000000 0 0 0 0 0 0 0 0 00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Id O P Q R S T U V W X Y Z a RW Field Value Id Value Description Disabled 0 Read: channel disabled Enabled 1 Read: channel enabled Clear 1 Write: disable channel Disabled 0 Read: channel disabled Enabled 1
22 PPI — Programmable peripheral interconnect Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 Id f e d c b a Z Y X W V U T S R Q P O N M L K J Reset 0x00000000 0 0 0 0 0 0 0 0 000000000000000000 Id RW Field b RW CH27 c Value Id Value Disabled 0 Read: channel disabled Enabled 1 Read: channel enabled Clear 1 Write: disable channel Disabled 0 Read: channel disabled Enabled 1 Read: channel enabled Clear 1 Write: disable channel Disabled 0
22 PPI — Programmable peripheral interconnect Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id Reset 0x00000000 Id RW Field A 0 Value Id AA A A A A A A AAAA A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value RW EEP Description Pointer to event register. Accepts only addresses to registers from the Event group. 22.2.7 CH[1].
22 PPI — Programmable peripheral interconnect Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id Reset 0x00000000 Id RW Field A 0 Value Id AA A A A A A A AAAA A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value RW TEP Description Pointer to task register. Accepts only addresses to registers from the Task group. 22.2.12 CH[4].
22 PPI — Programmable peripheral interconnect Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id Reset 0x00000000 Id RW Field A 0 Value Id AA A A A A A A AAAA A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value RW EEP Description Pointer to event register. Accepts only addresses to registers from the Event group. 22.2.17 CH[6].
22 PPI — Programmable peripheral interconnect Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id Reset 0x00000000 Id RW Field A 0 Value Id AA A A A A A A AAAA A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value RW TEP Description Pointer to task register. Accepts only addresses to registers from the Task group. 22.2.22 CH[9].
22 PPI — Programmable peripheral interconnect Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id Reset 0x00000000 Id RW Field A 0 Value Id AA A A A A A A AAAA A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value RW EEP Description Pointer to event register. Accepts only addresses to registers from the Event group. 22.2.27 CH[11].
22 PPI — Programmable peripheral interconnect Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id Reset 0x00000000 Id RW Field A 0 Value Id AA A A A A A A AAAA A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value RW TEP Description Pointer to task register. Accepts only addresses to registers from the Task group. 22.2.32 CH[14].
22 PPI — Programmable peripheral interconnect Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id Reset 0x00000000 Id RW Field A 0 Value Id AA A A A A A A AAAA A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value RW EEP Description Pointer to event register. Accepts only addresses to registers from the Event group. 22.2.37 CH[16].
22 PPI — Programmable peripheral interconnect Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id Reset 0x00000000 Id RW Field A 0 Value Id AA A A A A A A AAAA A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value RW TEP Description Pointer to task register. Accepts only addresses to registers from the Task group. 22.2.42 CH[19].
22 PPI — Programmable peripheral interconnect Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id f e d c b a Z Y XWVU T S R Q P O N M L K J Reset 0x00000000 0 0 0 0 0 0 0 0 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Id H I J K L M N O P Q R S T U V W X Y RW Field Value Id Value Description Excluded 0 Exclude Included 1 Include Excluded 0 Exclude Included 1 Include Excluded 0 Exclude Included 1 Include Ex
22 PPI — Programmable peripheral interconnect Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id f e d c b a Z Y XWVU T S R Q P O N M L K J Reset 0x00000000 0 0 0 0 0 0 0 0 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Id RW Field Z RW CH25 a b c d e f Value Id Value Description Included 1 Include Excluded 0 Exclude Included 1 Include Excluded 0 Exclude Included 1 Include Excluded 0 Exclude Included 1 Include Excl
22 PPI — Programmable peripheral interconnect Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id f e d c b a Z Y X W VU T S R Q P O N M L K J Reset 0x00000000 0 0 0 0 0 0 0 0 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Id I J K L M N O P Q R S T U V W X Y Z RW Field Value Id Value Description Included 1 Include Excluded 0 Exclude Included 1 Include Excluded 0 Exclude Included 1 Include Excluded 0 Exclude Inc
22 PPI — Programmable peripheral interconnect Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id f e d c b a Z Y XWVU T S R Q P O N M L K J Reset 0x00000000 0 0 0 0 0 0 0 0 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Id RW Field a RW CH26 b c d e f Value Id Value Excluded 0 Exclude Included 1 Include Excluded 0 Exclude Included 1 Include Excluded 0 Exclude Included 1 Include Excluded 0 Exclude Included 1 Include
22 PPI — Programmable peripheral interconnect Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id f e d c b a Z Y X W VUT S RQP O N M L K J Reset 0x00000000 0 0 0 0 0 0 0 0 000000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Id RW Field J RW CH9 K L M N O P Q R S T U V W X Y Z a b Value Id Value Description Excluded 0 Exclude Included 1 Include Excluded 0 Exclude Included 1 Include Excluded 0 Exclude Included 1 Include
22 PPI — Programmable peripheral interconnect Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id f e d c b a Z Y X W VU T S R Q P O N M L K J Reset 0x00000000 0 0 0 0 0 0 0 0 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Id c d e f RW Field Value Id Value Description Excluded 0 Exclude Included 1 Include Excluded 0 Exclude Included 1 Include Excluded 0 Exclude Included 1 Include Excluded 0 Exclude Included 1 Include
22 PPI — Programmable peripheral interconnect Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id f e d c b a Z Y XWVU T S R Q P O N M L K J Reset 0x00000000 0 0 0 0 0 0 0 0 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Id L M N O P Q R S T U V W X Y Z a b c RW Field Value Id Value Description Excluded 0 Exclude Included 1 Include Excluded 0 Exclude Included 1 Include Excluded 0 Exclude Included 1 Include Ex
22 PPI — Programmable peripheral interconnect Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id f e d c b a Z Y XWVU T S R Q P O N M L K J Reset 0x00000000 0 0 0 0 0 0 0 0 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Id RW Field d RW CH29 e f Value Id Value Description Included 1 Include Excluded 0 Exclude Included 1 Include Excluded 0 Exclude Included 1 Include Excluded 0 Exclude Included 1 Include I H G F E D C B
22 PPI — Programmable peripheral interconnect Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id f e d c b a Z Y X W VU T S R Q P O N M L K J Reset 0x00000000 0 0 0 0 0 0 0 0 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Id M N O P Q R S T U V W X Y Z a b c d RW Field Value Id Value Description Included 1 Include Excluded 0 Exclude Included 1 Include Excluded 0 Exclude Included 1 Include Excluded 0 Exclude Inc
22 PPI — Programmable peripheral interconnect Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id f e d c b a Z Y XWVU T S R Q P O N M L K J Reset 0x00000000 0 0 0 0 0 0 0 0 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Id RW Field e RW CH30 f Value Id Value Excluded 0 Exclude Included 1 Include Excluded 0 Exclude Included 1 Include I H G F E D C B A Description Include or exclude channel 30 RW CH31 Include or exclude channel
22 PPI — Programmable peripheral interconnect Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id f e d c b a Z Y X W VUT S RQPO N M L K J Reset 0x00000000 0 0 0 0 0 0 0 0 0000000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Id RW Field N RW CH13 O P Q R S T U V W X Y Z a b c d e f Value Id Value Description Excluded 0 Exclude Included 1 Include Excluded 0 Exclude Included 1 Include Excluded 0 Exclude Included 1 Include
22 PPI — Programmable peripheral interconnect Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id f e d c b a Z Y X W VU T S R Q P O N M L K J Reset 0x00000000 0 0 0 0 0 0 0 0 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Id RW Field Value Id Value Description Excluded 0 Exclude Included 1 Include I H G F E D C B A 22.2.50 FORK[0].
22 PPI — Programmable peripheral interconnect Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id Reset 0x00000000 Id RW Field A RW TEP 0 Value Id AA A A A A A A AAAA A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Description Pointer to task register 22.2.55 FORK[5].
22 PPI — Programmable peripheral interconnect 22.2.60 FORK[10].TEP Address offset: 0x938 Channel 10 task end-point Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id Reset 0x00000000 Id RW Field A RW TEP 0 Value Id AA A A A A A A AAAA A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Description Pointer to task register 22.2.61 FORK[11].
22 PPI — Programmable peripheral interconnect Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id Reset 0x00000000 Id RW Field A RW TEP 0 Value Id AA A A A A A A AAAA A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Description Pointer to task register 22.2.66 FORK[16].
22 PPI — Programmable peripheral interconnect 22.2.71 FORK[21].TEP Address offset: 0x964 Channel 21 task end-point Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id Reset 0x00000000 Id RW Field A RW TEP 0 Value Id AA A A A A A A AAAA A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Description Pointer to task register 22.2.72 FORK[22].
22 PPI — Programmable peripheral interconnect Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id Reset 0x00000000 Id RW Field A RW TEP 0 Value Id AA A A A A A A AAAA A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Description Pointer to task register 22.2.77 FORK[27].
22 PPI — Programmable peripheral interconnect Page 204
23 RADIO — 2.4 GHz Radio 23 RADIO — 2.4 GHz Radio The RADIO contains a 2.4 GHz radio receiver and a 2.4 GHz radio transmitter that is compatible with Nordic's proprietary 1 Mbps and 2 Mbps radio modes in addition to 1 Mbps and 2 Mbps Bluetooth® low energy mode. EasyDMA in combination with an automated packet assembler and packet disassembler, and an automated CRC generator and CRC checker, makes it very easy to configure and use the RADIO. See Figure 29: RADIO block diagram on page 205 for details.
23 RADIO — 2.4 GHz Radio In addition, the S0INCL field in PCNF0 determines if S0 is present in RAM at all if its length is zero. If present, one byte is allocated in RAM. The size of S0 is configured through the S0LEN field in PCNF0. The size of LENGTH is configured through the LFLEN field in PCNF0. The size of S1 is configured through the S1LEN field in PCNF0. The size of the payload is configured through the value in RAM corresponding to the LENGTH field.
23 RADIO — 2.4 GHz Radio The byte ordering on air is always Least Significant Byte First for the ADDRESS and PAYLOAD fields and Most Significant Byte First for the CRC field. The ADDRESS fields are always transmitted and received least significant bit first on-air. The CRC field is always transmitted and received Most Significant Bit first. The bitendian, i.e. which order the bits are sent and received in, of the S0, LENGTH, S1 and PAYLOAD fields can be configured via the ENDIAN in PCNF1.
23 RADIO — 2.4 GHz Radio D0 D4 D7 Data out + Position 0 1 2 + 3 4 5 6 Data in Figure 32: Data whitening and de-whitening Whitening and de-whitening will be performed over the whole packet (except for the preamble and the address field). The linear feedback shift register, illustrated in Figure 32: Data whitening and de-whitening on page 208 can be initialised via the DATAWHITEIV register. 23.6 CRC The CRC generator in the RADIO calculates the CRC over the whole packet excluding the preamble.
23 RADIO — 2.4 GHz Radio The status of the CRC check can be read from the CRCSTATUS register after a packet has been received. 23.7 Radio states The RADIO can enter a number of states. The RADIO can enter the states described the table below. An overview state diagram for the RADIO is illustrated in Figure 34: Radio states on page 209. This figure shows how the tasks and events relate to the RADIO's operation. The RADIO does not prevent a task from being triggered from the wrong state.
23 RADIO — 2.4 GHz Radio TX A CRC ADDRESS PAYLOAD (carrier) 3 DISABLE 2 START 1 TXEN Lifeline S0 L S1 TXDISABLE END P READY (carrier) TXIDLE DISABLED TXIDLE Transmitter TXRU PAYLOAD State the RADIO will by default transmit '1's between READY and START, and between END and DISABLED. What is transmitted can be programmed through the DTX field in the MODECNF0 register.
PAYLOAD CRC (carrier) P A S0 L S1 PAYLOAD CRC (carrier) DISABLED PAYLOAD TXDISABLE PAYLOAD S0 L S1 TX ADDRESS A ADDRESS 2 3 START TXEN START 1 DISABLE Lifeline READY P TXIDLE END TX Transmitter TXRU END State 23 RADIO — 2.4 GHz Radio Figure 37: Transmission of multiple packets 23.9 Receive sequence Before the RADIO is able to receive a packet, it must first ramp up in RX mode See RXRU in Figure 34: Radio states on page 209 and Figure 38: Receive sequence on page 211.
RX A PAYLOAD CRC ADDRESS Lifeline S0 L S1 DISABLED P READY ’X’ RXDISABLE PAYLOAD Reception RXRU END State 23 RADIO — 2.
23 RADIO — 2.4 GHz Radio interval as specified in the TIFS register as long as TIFS is not specified to be shorter than the RADIO’s turnaround time, i.e. the time needed to switch off the receiver, and switch back on the transmitter. TIFS is only enforced if END_DISABLE and DISABLED_TXEN or END_DISABLE and DISABLED_RXEN shortcuts are enabled. TIFS is only qualified for use in BLE_1MBIT mode, and default ramp-up mode. 23.
RX DISABLED 3 DISABLE BCC = 12 + 16 BCSTART START CRC BCMATCH BCMATCH READY 2 BCC = 12 2 PAYLOAD 1 RXEN 1 S0 L S1 PAYLOAD Lifeline This example assumes that the combined length of S0, Length (L) and S1 is 12 bits. A ADDRESS Reception 0 ’X’ P RXDISABLE END RXRU BCSTOP State 23 RADIO — 2.4 GHz Radio Figure 41: Bit counter example 23.14 Registers Table 40: Instances Base address Peripheral Instance Description 0x40001000 RADIO RADIO 2.
23 RADIO — 2.
23 RADIO — 2.
23 RADIO — 2.
23 RADIO — 2.
23 RADIO — 2.4 GHz Radio Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id L K Reset 0x00000000 Id RW Field 0 I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Enabled 1 Description Read: Enabled 23.14.
23 RADIO — 2.4 GHz Radio Packet pointer Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id Reset 0x00000000 Id RW Field A RW PACKETPTR 0 Value Id AA A A A A A A AAAA A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Description Packet pointer Packet address to be used for the next transmission or reception.
23 RADIO — 2.4 GHz Radio Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id A A A A Reset 0x00000000 Id RW Field A RW MODE 0 Value Id 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Description Radio data rate and modulation setting. The radio supports Frequency-shift Keying (FSK) modulation.
23 RADIO — 2.4 GHz Radio Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id E D Reset 0x00000000 Id RW Field 0 C C C B B B B B B B B A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Enabled 1 Description Enable 23.14.
23 RADIO — 2.4 GHz Radio 23.14.18 TXADDRESS Address offset: 0x52C Transmit address select Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id A A A Reset 0x00000000 Id RW Field A RW TXADDRESS 0 Value Id 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Description Transmit address select Logical address to be used when transmitting a packet. 23.14.
23 RADIO — 2.4 GHz Radio Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id B Reset 0x00000000 Id B RW Field 0 A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Three 3 Description Include 0 CRC calculation includes address field Skip 1 CRC calculation does not include address field.
23 RADIO — 2.4 GHz Radio Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id A A A A A A A Reset 0x00000000 Id RW Field A R 0 Value Id RSSISAMPLE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value [0..127] Description RSSI sample RSSI sample result. The value of this register is read as a positive value while the actual received signal strength is a negative value.
23 RADIO — 2.4 GHz Radio 23.14.28 DAB[0] Address offset: 0x600 Device address base segment 0 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id Reset 0x00000000 Id RW Field A RW DAB 0 Value Id AA A A A A A A AAAA A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Description Device address base segment 0 23.14.
23 RADIO — 2.4 GHz Radio Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id Reset 0x00000000 Id RW Field A RW DAB 0 Value Id AA A A A A A A AAAA A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Description Device address base segment 5 23.14.
23 RADIO — 2.4 GHz Radio 23.14.39 DAP[3] Address offset: 0x62C Device address prefix 3 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id A A A A A A A A A A A A A A A A Reset 0x00000000 Id RW Field A RW DAP 0 Value Id 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Description Device address prefix 3 23.14.
23 RADIO — 2.
23 RADIO — 2.4 GHz Radio Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id C C Reset 0x00000200 Id RW Field C RW DTX 0 Value Id A 0000000000000000000001000000000 Value Description Default TX value Specifies what the RADIO will transmit when it is not started, i.e. between: RADIO.EVENTS_READY and RADIO.TASKS_START RADIO.EVENTS_END and RADIO.TASKS_START RADIO.EVENTS_END and RADIO.
23 RADIO — 2.4 GHz Radio Symbol Description ITX,MINUS8dBM TX only run current PRF = -8 dBm Min. Typ. 8.4 Max. Units mA ITX,MINUS12dBM,DCDC TX only run current DCDC, 3V PRF = -12 dBm 3.5 mA ITX,MINUS12dBM TX only run current PRF = -12 dBm 7.7 mA ITX,MINUS16dBM,DCDC TX only run current DCDC, 3V PRF = -16 dBm 3.3 mA ITX,MINUS16dBM TX only run current PRF = -16 dBm 7.3 mA ITX,MINUS20dBM,DCDC TX only run current DCDC, 3V PRF = -20 dBm 3.
23 RADIO — 2.4 GHz Radio Symbol Description PSENS,IT,SP,2M,BLE Sensitivity, 2Msps BLE ideal transmitter, Packet length Min. Typ. Max. Units -93 dBm -93 dBm <=37bytes PSENS,DT,SP,2M,BLE Sensitivity, 2Msps BLE dirty transmitter, Packet length <=37bytes PSENS,IT,LP,2M,BLE Sensitivity, 2Msps BLE ideal transmitter >= 128bytes -92 dBm PSENS,DT,LP,2M,BLE Sensitivity, 2Msps BLE dirty transmitter, Packet length >= -92 dBm 128bytes 23.15.
23 RADIO — 2.4 GHz Radio Symbol Description PIMD,2M,BLE IMD performance, BLE 2 Msps (6 MHz, 8 MHz, and 10 MHz Min. Typ. Max. -32 Units dBm offset) 23.15.8 Radio timing Symbol Description tTXEN Time between TXEN task and READY event after channel Min. Typ. Max.
24 TIMER — Timer/counter 24 TIMER — Timer/counter The TIMER can operate in two modes: timer and counter. CLEAR CAPTURE[0..n] STOP START COUNT TIMER TIMER Core Increment BITMODE Counter PCLK1M Prescaler PCLK16M fTIMER PRESCALER CC[0..n] MODE COMPARE[0..n] Figure 42: Block schematic for timer/counter The timer/counter runs on the high-frequency clock source (HFCLK) and includes a four-bit (1/2X) prescaler that can divide the timer input clock from the HFCLK controller.
24 TIMER — Timer/counter When the timer is incremented beyond its maximum value the Counter register will overflow and the TIMER will automatically start over from zero. The Counter register can be cleared, that is, its internal value set to zero explicitly, by triggering the CLEAR task. The TIMER implements multiple capture/compare registers.
24 TIMER — Timer/counter Register Offset TASKS_STOP 0x004 Description Stop Timer TASKS_COUNT 0x008 Increment Timer (Counter mode only) TASKS_CLEAR 0x00C Clear time TASKS_SHUTDOWN 0x010 Shut down timer TASKS_CAPTURE[0] 0x040 Capture Timer value to CC[0] register TASKS_CAPTURE[1] 0x044 Capture Timer value to CC[1] register TASKS_CAPTURE[2] 0x048 Capture Timer value to CC[2] register TASKS_CAPTURE[3] 0x04C Capture Timer value to CC[3] register TASKS_CAPTURE[4] 0x050 Capture Timer v
24 TIMER — Timer/counter Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id L K J Reset 0x00000000 Id F RW Field 0 I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Description Disabled 0 Disable shortcut Enabled 1 Enable shortcut RW COMPARE5_CLEAR Shortcut between COMPARE[5] event and CLEAR task See EVENTS_COMPARE[5] and TASKS_CLEAR G Disabled 0 Disable shortcut Enabled 1 Enable shortc
24 TIMER — Timer/counter Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id F E D C B A Reset 0x00000000 Id RW Field 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Description Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled See EVENTS_COMPARE[2] D RW COMPARE3 Write '1' to Enable interrupt for COMPARE[3] event See EVENTS_COMPARE[3] E Set 1 Enable Disabled 0 Read: Disabled Enabled 1
24 TIMER — Timer/counter Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id F E D C B A Reset 0x00000000 Id F RW Field 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Description Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW COMPARE5 Write '1' to Disable interrupt for COMPARE[5] event See EVENTS_COMPARE[5] Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled 24.5.
24 TIMER — Timer/counter Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id Reset 0x00000000 Id RW Field A RW CC 0 Value Id AA A A A A A A AAAA A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Description Capture/Compare value Only the number of bits indicated by BITMODE will be used by the TIMER. 24.5.
24 TIMER — Timer/counter Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id Reset 0x00000000 Id 0 RW Field Value Id AA A A A A A A AAAA A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Description Only the number of bits indicated by BITMODE will be used by the TIMER. 24.5.
25 RTC — Real-time counter 25 RTC — Real-time counter The Real-time counter (RTC) module provides a generic, low power timer on the low-frequency clock source (LFCLK). 32.768 kHz START STOP CLEAR TRIGOVRFLW task PRESCALER event TICK event OVRFLW COUNTER task RTC task task CC[0:3] COMPARE[0..
25 RTC — Real-time counter 10009.576 µs counter period 2. Desired COUNTER frequency 8 Hz (125 ms counter period) PRESCALER = round(32.768 kHz / 8 Hz) – 1 = 4095 fRTC = 8 Hz 125 ms counter period Table 44: RTC resolution versus overflow Prescaler 0 28-1 212-1 Counter resolution 30.517 μs 7812.5 μs 125 ms Overflow 512 seconds 131072 seconds 582.542 hours 25.3 COUNTER register The COUNTER increments on LFCLK when the internal PRESCALER register (<>) is 0x00.
25 RTC — Real-time counter Using the RTC TICK event rather than the SysTick allows the CPU to be powered down while still keeping RTOS scheduling active. Important: The TICK event is disabled by default. 25.6 Event control feature To optimize RTC power consumption, events in the RTC can be individually disabled to prevent PCLK16M and HFCLK being requested when those events are triggered. This is managed using the EVTEN register.
25 RTC — Real-time counter SysClk LFClk PRESC 0x000 COUNTER X 0x000000 CLEAR CC[0] 0x000000 COMPARE[0] • 0 Figure 47: Timing diagram - COMPARE_CLEAR If a CC register is N and the COUNTER value is N when the START task is set, this will not trigger a COMPARE event. SysClk LFClk PRESC 0x000 COUNTER N-1 N N+1 START • CC[0] N COMPARE[0] 0 Figure 48: Timing diagram - COMPARE_START COMPARE occurs when a CC register is N and the COUNTER value transitions from N-1 to N.
25 RTC — Real-time counter SysClk LFClk PRESC COUNTER 0x000 N-1 N N+1 N+2 > 62.5 ns CC[0] X N+2 COMPARE[0] • 0 1 Figure 50: Timing diagram - COMPARE_N+2 If the COUNTER is N, writing N or N+1 to a CC register may not trigger a COMPARE event.
25 RTC — Real-time counter Table 45: RTC jitter magnitudes on tasks Task CLEAR, STOP, START, TRIGOVRFLOW Delay +15 to 46 μs Table 46: RTC jitter magnitudes on events Operation/Function START to COUNTER increment COMPARE to COMPARE 22 Jitter +/- 15 μs +/- 62.5 ns 1. CLEAR and STOP (and TRIGOVRFLW; not shown) will be delayed as long as it takes for the peripheral to clock a falling edge and rising of the LFCLK. This is between 15.2585 µs and 45.
25 RTC — Real-time counter SysClk First tick LFClk PRESC COUNTER START 0x000 X+1 X X+2 X+3 >= ~15 us 0 or more SysClk before Figure 55: Timing diagram - JITTER_STARTSysClk First tick LFClk PRESC COUNTER 0x000 X+1 X X+2 <= ~250 us START Figure 56: Timing diagram - JITTER_START+ 25.9 Reading the COUNTER register To read the COUNTER register, the internal <> value is sampled.
25 RTC — Real-time counter Base address Peripheral Instance Description Configuration 0x40024000 RTC RTC2 Real-time counter 2 CC[0..
25 RTC — Real-time counter Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id F E D C Reset 0x00000000 Id RW Field E RW COMPARE2 0 Value Id B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Description Write '1' to Enable interrupt for COMPARE[2] event See EVENTS_COMPARE[2] F Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW COMPARE3 Write '1' to Enable interrupt for COMPARE[3] event See EVENTS_CO
25 RTC — Real-time counter 25.10.
25 RTC — Real-time counter Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id F E D C Reset 0x00000000 Id D RW Field 0 B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Description Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW COMPARE1 Write '1' to Enable event routing for COMPARE[1] event See EVENTS_COMPARE[1] E Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW COMPARE2 Wr
25 RTC — Real-time counter Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 Id F E D C Reset 0x00000000 Id RW Field F RW COMPARE3 0 Value Id B A 0 0 0 0 0 0 0 000000000000000000 Value 5 4 3 2 1 0 0 0 0 0 0 0 Description Write '1' to Disable event routing for COMPARE[3] event See EVENTS_COMPARE[3] Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled 25.10.
25 RTC — Real-time counter Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 Id RW Field A RW COMPARE 0 Value Id 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Description Compare value 25.10.
26 RNG — Random number generator 26 RNG — Random number generator The Random number generator (RNG) generates true non-deterministic random numbers based on internal thermal noise that are suitable for cryptographic purposes. The RNG does not require a seed value. START Random number generator STOP VALRDY VALUE Figure 58: Random number generator The RNG is started by triggering the START task and stopped by triggering the STOP task.
26 RNG — Random number generator Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id A Reset 0x00000000 Id RW Field A RW VALRDY_STOP 0 Value Id 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Description Shortcut between VALRDY event and STOP task See EVENTS_VALRDY and TASKS_STOP Disabled 0 Disable shortcut Enabled 1 Enable shortcut 26.3.
26 RNG — Random number generator Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id A A A A A A A A Reset 0x00000000 Id RW Field A R 0 Value Id VALUE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Description [0..255] Generated random number 26.4 Electrical specification 26.4.1 RNG Electrical Specification Symbol Description IRNG Run current, CPU sleeping. Min. Typ. 500 Max.
27 TEMP — Temperature sensor 27 TEMP — Temperature sensor The temperature sensor measures die temperature over the temperature range of the device. Linearity compensation can be implemented if required by the application. Listed here are the main features for TEMP: • • Temperature range is greater than or equal to operating temperature of the device Resolution is 0.25 degrees TEMP is started by triggering the START task.
27 TEMP — Temperature sensor 27.1.1 INTENSET Address offset: 0x304 Enable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id A Reset 0x00000000 Id RW Field A RW DATARDY 0 Value Id 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Description Write '1' to Enable interrupt for DATARDY event See EVENTS_DATARDY Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled 27.1.
27 TEMP — Temperature sensor Slope of 2nd piece wise linear function Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id A A A A A A A A A A A A Reset 0x00000343 Id RW Field A RW A1 0 Value Id 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 1 1 Value Description Slope of 2nd piece wise linear function 27.1.
27 TEMP — Temperature sensor Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id A A A A A A A A A A A A A A Reset 0x00003FCC Id RW Field A RW B0 0 Value Id 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 0 0 Value Description y-intercept of 1st piece wise linear function 27.1.
27 TEMP — Temperature sensor 27.1.16 T0 Address offset: 0x560 End point of 1st piece wise linear function Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id A A A A A A A A Reset 0x000000E2 Id RW Field A RW T0 0 Value Id 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 1 0 Value Description End point of 1st piece wise linear function 27.1.
27 TEMP — Temperature sensor 27.2 Electrical specification 27.2.1 Temperature Sensor Electrical Specification Symbol Description tTEMP Time required for temperature measurement Min. Typ. Max. TTEMP,RANGE Temperature sensor range -40 85 °C TTEMP,ACC Temperature sensor accuracy -5 5 °C TTEMP,RES Temperature sensor resolution 0.25 TTEMP,STB Sample to sample stability at constant device temperature +/-0.25 TTEMP,OFFST Sample offset at 25°C 36 -2.5 Page 263 Units µs °C °C 2.
28 ECB — AES electronic codebook mode encryption 28 ECB — AES electronic codebook mode encryption The AES electronic codebook mode encryption (ECB) can be used for a range of cryptographic functions like hash generation, digital signatures, and keystream generation for data encryption/decryption. The ECB encryption block supports 128 bit AES encryption (encryption only, not decryption).
28 ECB — AES electronic codebook mode encryption 28.
28 ECB — AES electronic codebook mode encryption Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id B A Reset 0x00000000 Id 0 RW Field 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Description Enabled 1 Read: Enabled 28.4.
29 CCM — AES CCM mode encryption 29 CCM — AES CCM mode encryption Cipher block chaining - message authentication code (CCM) mode is an authenticated encryption algorithm designed to provide both authentication and confidentiality during data transfer. CCM combines counter mode encryption and CBC-MAC authentication. The CCM terminology "Message authentication code (MAC)" is called the "Message integrity check (MIC)" in 'Bluetooth terminology and also in this document.
29 CCM — AES CCM mode encryption 29.1 Shared resources The CCM shares registers and other resources with other peripherals that have the same ID as the CCM. The user must therefore disable all peripherals that have the same ID as the CCM before the CCM can be configured and used. Disabling a peripheral that have the same ID as the CCM will not reset any of the registers that are shared with the CCM.
29 CCM — AES CCM mode encryption SCRATCHPTR OUTPTR Unencrypted packet H L INPTR RFU PL MODE = DECRYPTION Encrypted packet H L+4 RFU Scratch area EPL AES CCM H: Header (S0) L: Length RFU: reserved for future use (S1) PL: unencrypted payload EPL: encrypted payload CCM data structure MIC CNFPTR Figure 61: Decryption 29.
29 CCM — AES CCM mode encryption SHORTCUT ENDKSGEN CRYPT key-stream generation AES CCM KSGEN encryption ENDCRYPT PPI READY RADIO RU P A H L RFU EPL MIC CRC TXEN END READY RU: Ramp-up of RADIO P: Preamble A: Address START SHORTCUT H: Header (S0) L: Length RFU: reserved for future use (S1) EPL: encrypted payload Figure 63: On-the-fly encryption using a PPI connection 29.
29 CCM — AES CCM mode encryption key-stream generation AES CCM KSGEN decryption ENDKSGEN CRYPT ENDCRYPT PPI PPI READY RADIO ADDRESS RU P A H L RFU EPL MIC RXEN CRC END START READY RU: Ramp-up of RADIO P: Preamble A: Address SHORTCUT H: Header (S0) L: Length RFU: reserved for future use (S1) EPL: encrypted payload : RADIO receiving noise Figure 65: On-the-fly decryption using a PPI connection between the READY event in the RADIO and the KSGEN task in the AES CCM 29.
29 CCM — AES CCM mode encryption Property Address offset Description Important: MIC is not added to empty packets 29.8 EasyDMA and ERROR event The CCM implements an EasyDMA mechanism for reading and writing to the RAM. In some scenarios where the CPU and other DMA enabled peripherals are accessing the RAM at the same time, the CCM DMA could experience some bus conflicts which may also result in an error during encryption. If this happens, the ERROR event will be generated.
29 CCM — AES CCM mode encryption 29.9.
29 CCM — AES CCM mode encryption Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id A Reset 0x00000000 Id RW Field A R 0 Value Id 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value MICSTATUS Description The result of the MIC check performed during the previous decryption operation CheckFailed 0 MIC check failed CheckPassed 1 MIC check passed 29.9.
29 CCM — AES CCM mode encryption Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id Reset 0x00000000 Id RW Field A RW INPTR 0 Value Id AA A A A A A A AAAA A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Description Input pointer 29.9.
30 AAR — Accelerated address resolver 30 AAR — Accelerated address resolver Accelerated address resolver is a cryptographic support function for implementing the "Resolvable Private Address Resolution Procedure" described in the Bluetooth Core specification v4.0. "Resolvable private address generation" should be achieved using ECB and is not supported by AAR. The procedure allows two devices that share a secret key to generate and resolve a hash based on their device address.
30 AAR — Accelerated address resolver resolvable address is located. The resolution time will also be affected by RAM accesses performed by other peripherals and the CPU. See the Electrical specifications for more information about resolution time. The AAR will only do a comparison of the received address to those programmed in the module. And not check what type of address it actually is.
30 AAR — Accelerated address resolver 30.
30 AAR — Accelerated address resolver Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id C B A Reset 0x00000000 Id RW Field A RW END 0 Value Id 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Description Write '1' to Disable interrupt for END event See EVENTS_END B Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW RESOLVED Write '1' to Disable interrupt for RESOLVED event See EVENTS_RESOLVED C C
30 AAR — Accelerated address resolver Pointer to IRK data structure Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id Reset 0x00000000 Id RW Field A RW IRKPTR AA A A A A A A AAAA A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Description Pointer to the IRK data structure 30.6.
31 SPIM — Serial peripheral interface master with EasyDMA 31 SPIM — Serial peripheral interface master with EasyDMA The SPI master can communicate with multiple slaves using individual chip select signals for each of the slave devices attached to a bus. Listed here are the main features for the SPIM STOP Three SPIM instances SPI mode 0-3 EasyDMA direct transfer to/from RAM for both SPI Slave and SPI Master Individual selection of IO pin for each SPI signal START • • • • SPIM GPIO RAM PSEL.MOSI TXD.
31 SPIM — Serial peripheral interface master with EasyDMA Disabling a peripheral that has the same ID as the SPI will not reset any of the registers that are shared with the SPI. It is therefore important to configure all relevant SPI registers explicitly to secure that it operates correctly. See the Instantiation table in Instantiation on page 24 for details on peripherals and their IDs. 31.
31 SPIM — Serial peripheral interface master with EasyDMA //replace 'Channel' below by the specific data channel you want to use, // for instance 'NRF_SPIM->RXD', 'NRF_TWIM->RXD', etc. Channel.MAXCNT = BUFFER_SIZE; Channel.PTR = &MyArrayList; Channel.
31 SPIM — Serial peripheral interface master with EasyDMA CSN SCK MOSI 0 1 2 n ORC ORC MISO A B C m-2 m-1 m ENDRX ENDTX CPU 1 2 START Figure 71: SPI master transaction 31.4 Low power When putting the system in low power and the peripheral is not needed, lowest possible power consumption is achieved by stopping, and then disabling the peripheral.
31 SPIM — Serial peripheral interface master with EasyDMA 31.
31 SPIM — Serial peripheral interface master with EasyDMA Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id E Reset 0x00000000 Id RW Field A RW STOPPED 0 Value Id D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Description Write '1' to Enable interrupt for STOPPED event See EVENTS_STOPPED B Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW ENDRX Write '1' to Enable interrupt for ENDRX ev
31 SPIM — Serial peripheral interface master with EasyDMA Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id E Reset 0x00000000 Id E RW Field 0 D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Description Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW STARTED Write '1' to Disable interrupt for STARTED event See EVENTS_STARTED Clear 1 Disable Disabled 0 Read: Disabled En
31 SPIM — Serial peripheral interface master with EasyDMA Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id B A A A A A Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Id RW Field A RW PIN B RW CONNECT Value Id Value Description [0..31] Pin number Connection Disconnected 1 Disconnect Connected 0 Connect 31.6.
31 SPIM — Serial peripheral interface master with EasyDMA 31.6.12 RXD.LIST Address offset: 0x540 EasyDMA list type Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id A A A Reset 0x00000000 Id RW Field A RW LIST 0 Value Id 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Description List type Disabled 0 Disable EasyDMA list ArrayList 1 Use array list 31.6.13 TXD.
31 SPIM — Serial peripheral interface master with EasyDMA 31.6.
31 SPIM — Serial peripheral interface master with EasyDMA Symbol Description tSPIM,RSCK,LD SCK rise time, low drivea Min. Typ. Max.
32 SPIS — Serial peripheral interface slave with EasyDMA 32 SPIS — Serial peripheral interface slave with EasyDMA SPI slave (SPIS) is implemented with EasyDMA support for ultra low power serial communication from an external SPI master. EasyDMA in conjunction with hardware-based semaphore mechanisms removes all real-time requirements associated with controlling the SPI slave from a low priority CPU execution context. PSEL.CSN PSEL.MISO PSEL.MOSI PSEL.
32 SPIS — Serial peripheral interface slave with EasyDMA If the TXD.PTR and the RXD.PTR are not pointing to the Data RAM region, an EasyDMA transfer may result in a HardFault or RAM corruption. See Memory on page 23 for more information about the different memory regions. 32.3 SPI slave operation SPI slave uses two memory pointers, RXD.PTR and TXD.PTR, that point to the RXD buffer (receive buffer) and TXD buffer (transmit buffer) respectively.
32 SPIS — Serial peripheral interface slave with EasyDMA The RXD.AMOUNT and TXD.AMOUNT registers are updated when a granted transaction is completed. The TXD.AMOUNT register indicates how many bytes were read from the TX buffer in the last transaction, that is, ORC (over-read) characters are not included in this number. Similarly, the RXD.AMOUNT register indicates how many bytes were written into the RX buffer in the last transaction. The ENDRX event is generated when the RX buffer has been filled.
32 SPIS — Serial peripheral interface slave with EasyDMA slave itself is temporarily disabled, or if the device temporarily enters System OFF. This configuration must be retained in the GPIO for the selected I/Os as long as the SPI slave is to be recognized by an external SPI master. The MISO line is set in high impedance as long as the SPI slave is not selected with CSN. Only one peripheral can be assigned to drive a particular GPIO pin at a time. Failing to do so may result in unpredictable behavior.
32 SPIS — Serial peripheral interface slave with EasyDMA Register Offset Description DEF 0x55C Default character. Character clocked out in case of an ignored transaction. ORC 0x5C0 Over-read character 32.5.
32 SPIS — Serial peripheral interface slave with EasyDMA Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id C Reset 0x00000000 Id RW Field 0 B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Description Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled See EVENTS_ENDRX C RW ACQUIRED Write '1' to Disable interrupt for ACQUIRED event See EVENTS_ACQUIRED Clear 1 Disable Disabled 0 Read
32 SPIS — Serial peripheral interface slave with EasyDMA Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id A A A A Reset 0x00000000 Id RW Field 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Description Disabled 0 Disable SPI slave Enabled 2 Enable SPI slave 32.5.
32 SPIS — Serial peripheral interface slave with EasyDMA Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id B A A A A A Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Id RW Field A RW PIN B RW CONNECT Value Id Value Description [0..31] Pin number Connection Disconnected 1 Disconnect Connected 0 Connect 32.5.12 PSEL.
32 SPIS — Serial peripheral interface slave with EasyDMA Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id Reset 0x00000000 Id RW Field A RW RXDPTR AA A A A A A A AAAA A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Description RXD data pointer 32.5.
32 SPIS — Serial peripheral interface slave with EasyDMA 32.5.21 TXDPTR ( Deprecated ) Address offset: 0x544 TXD data pointer Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id Reset 0x00000000 Id RW Field A RW TXDPTR AA A A A A A A AAAA A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Description TXD data pointer 32.5.
32 SPIS — Serial peripheral interface slave with EasyDMA Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id A A A A A A A A Reset 0x00000000 Id RW Field A R 0 Value Id 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value AMOUNT Description Number of bytes transmitted in last granted transaction 32.5.
32 SPIS — Serial peripheral interface slave with EasyDMA 32.6 Electrical specification 32.6.1 SPIS slave interface electrical specifications Symbol Description fSPIS Bit rates for SPIS27 Min. Typ. Max.
32 SPIS — Serial peripheral interface slave with EasyDMA Master Slave CSN (in) tSUCSN SCK CPOL=0 CPHA=0 tCSCK tWHSCK tWLSCK CPOL=1 CPHA=0 tHCSN tRSCK tFSCK CPOL=0 CPHA=1 CPOL=1 CPHA=1 tHMI tVSO tSUMI tASO MISO (in) MISO (out) tDISSO MSb LSb tHMO tVMO tHSI tSUSI MOSI (out) MOSI (in) tHSO MSb LSb Figure 76: Common SPIM and SPIS timing diagram Page 304
33 TWIM — I2C compatible two-wire interface master with EasyDMA 33 TWIM — I2C compatible two-wire interface master with EasyDMA TWI master with EasyDMA (TWIM) is a two-wire half-duplex master which can communicate with multiple slave devices connected to the same bus Listed here are the main features for TWIM: • • • • I2C compatible 100 kbps, 250 kbps, or 400 kbps Support for clock stretching EasyDMA The two-wire interface can communicate with a bi-directional wired-AND bus with two lines (SCL, SDA).
33 TWIM — I2C compatible two-wire interface master with EasyDMA VDD VDD TWI master (TWIM) SDA SCL R R TWI slave (EEPROM) TWI slave (Sensor) TWI slave Address = b1011001 Address = b1011000 Address = b1011011 SCL SDA SCL SDA SCL SDA Figure 78: A typical TWI setup comprising one master and three slaves This TWI master supports clock stretching performed by the slaves. The TWI master is started by triggering the STARTTX or STARTRX tasks, and stopped by triggering the STOP task.
33 TWIM — I2C compatible two-wire interface master with EasyDMA The Channel.MAXCNT register cannot be specified larger than the actual size of the buffer. If Channel.MAXCNT is specified larger than the size of the buffer, the EasyDMA channel may overflow the buffer. This array list does not provide a mechanism to explicitly specify where the next item in the list is located. Instead, it assumes that the list is organized as a linear array where items are located one after the other in RAM.
33 TWIM — I2C compatible two-wire interface master with EasyDMA STOPPED 4 STOP RESUME 3 SUSPEND STARTTX TXD.
33 TWIM — I2C compatible two-wire interface master with EasyDMA Note that the TWI master does not stop by itself when the RAM buffer is full, or when an error occurs. The STOP task must be issued, through the use of a local or PPI shortcut, or in software as part of the error handler. The TWI master cannot get stopped while it is suspended, so the STOP task has to be issued after the TWI master has been resumed. LASTRX 3 4 STOP SUSPEND RESUME 2 STARTRX RXD.
33 TWIM — I2C compatible two-wire interface master with EasyDMA STOPPED LASTTX 5 STOP STARTTX RESUME STARTRX TXD.MAXCNT = 2 SUSPEND RXD.MAXCNT = 1 STARTTX TXD.MAXCNT = 1 LASTRX SUSPENDED LASTTX TWI CPU Lifeline 4 ACK 3 1 STOP 0 ACK ACK ADDR WRITE 2 NACK 1 0 RESTART ADDR ACK Stretch READ 0 RESTART ACK ACK WRITE START ADDR Figure 83: A double repeated start sequence using the SUSPEND task to secure safe operation in low priority interrupts 33.
33 TWIM — I2C compatible two-wire interface master with EasyDMA Table 75: Register Overview Register Offset Description TASKS_STARTRX 0x000 Start TWI receive sequence TASKS_STARTTX 0x008 Start TWI transmit sequence TASKS_STOP 0x014 Stop TWI transaction. Must be issued while the TWI master is not suspended.
33 TWIM — I2C compatible two-wire interface master with EasyDMA Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id F Reset 0x00000000 Id F RW Field 0 D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Description Enabled 1 Enable shortcut RW LASTRX_STOP Shortcut between LASTRX event and STOP task See EVENTS_LASTRX and TASKS_STOP Disabled 0 Disable shortcut Enabled 1 Enable shortcut 33.8.
33 TWIM — I2C compatible two-wire interface master with EasyDMA Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id J Reset 0x00000000 Id RW Field A RW STOPPED 0 Value Id I H G F D A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Description Write '1' to Enable interrupt for STOPPED event See EVENTS_STOPPED D Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW ERROR Write '1' to Enable interrupt fo
33 TWIM — I2C compatible two-wire interface master with EasyDMA Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id J Reset 0x00000000 Id F RW Field 0 I H G F D A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Description Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW SUSPENDED Write '1' to Disable interrupt for SUSPENDED event See EVENTS_SUSPENDED G Clear 1 Disable Disabled 0
33 TWIM — I2C compatible two-wire interface master with EasyDMA Enable TWIM Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id A A A A Reset 0x00000000 Id RW Field A RW ENABLE 0 Value Id 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Description Enable or disable TWIM Disabled 0 Disable TWIM Enabled 6 Enable TWIM 33.8.7 PSEL.
33 TWIM — I2C compatible two-wire interface master with EasyDMA Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id Reset 0x00000000 Id RW Field A RW PTR AA A A A A A A AAAA A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Description Data pointer 33.8.11 RXD.
33 TWIM — I2C compatible two-wire interface master with EasyDMA Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id A A A A A A A A Reset 0x00000000 Id RW Field A RW MAXCNT 0 Value Id 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Description [1..255] Maximum number of bytes in transmit buffer 33.8.16 TXD.
33 TWIM — I2C compatible two-wire interface master with EasyDMA 33.9.2 Two Wire Interface Master (TWIM) timing specifications Symbol Description fTWIM,SCL,100kbps SCL clock frequency, 100 kbps Min. Typ. 100 Max.
34 TWIS — I2C compatible two-wire interface slave with EasyDMA 34 TWIS — I2C compatible two-wire interface slave with EasyDMA TWI slave with EasyDMA (TWIS) is compatible with I2C operating at 100 kHz and 400 kHz. The TWI transmitter and receiver implement EasyDMA. PSELSDA PSELSCK PSELSDA PREPARETX PREPARERX RXD (signal) STOPPED TXD (signal) SUSPEND WRITE RESUME RXD.PTR EasyDMA EasyDMA TXD.
34 TWIS — I2C compatible two-wire interface slave with EasyDMA PREPARETX PREPARERX ENABLE / STOPPED Unprepare TX, Unprepare RX IDLE STOP [ READ && (TX prepared) ] [ WRITE && (RX prepared) ] Restart sequence Stop sequence TX RX entry / Unprepare TX entry / Unprepare RX entry / TXSTARTED entry / RXSTARTED Figure 88: TWI slave state machine Table 76: TWI slave state machine symbols Symbol ENABLE PREPARETX STOP PREPARERX STOPPED RXSTARTED TXSTARTED TX prepared RX prepared Unprepare TX Unprepare
34 TWIS — I2C compatible two-wire interface slave with EasyDMA 34.1 Shared resources The TWI slave shares registers and other resources with other peripherals that have the same ID as the TWI slave. Therefore, you must disable all peripherals that have the same ID as the TWI slave before the TWI slave can be configured and used. Disabling a peripheral that has the same ID as the TWI slave will not reset any of the registers that are shared with the TWI slave.
34 TWIS — I2C compatible two-wire interface slave with EasyDMA forces the slave to send more than TXD.MAXCNT bytes, the slave will send the byte specified in the ORC register to the master instead. If this happens, an ERROR event will be generated. The EasyDMA configuration registers, see TXD.PTR etc., are latched when the TXSTARTED event is generated. The TWI slave can be forced to stop by triggering the STOP task. A STOPPED event will be generated when the TWI slave has stopped.
34 TWIS — I2C compatible two-wire interface slave with EasyDMA The TWI slave will generate the RXSTARTED event and clear the internal 'RX prepared' flag ('unprepare RX') when it enters the RX state. In this state the TWI slave will be able to receive the bytes sent by the TWI master. The TWI slave will consume IRX in this mode. The TWI slave will go back to the IDLE state if the TWI slave receives a restart command when it is in the RX state.
34 TWIS — I2C compatible two-wire interface slave with EasyDMA RESUME TXD.MAXCNT = 4 PREPARETX SUSPEND TXD.PTR = 0x20000010 STOPPED 3 2 PREPARERX RXD.MAXCNT = 2 RXD.PTR = 0x20000000 TXSTARTED READ WRITE RXSTARTED TWI CPU Lifeline 3 STOP NACK 2 ACK 1 1 ACK 0 ACK ADDR ACK READ 1 RESTART ACK 0 ACK ACK WRITE START ADDR Figure 91: A repeated start sequence, where the TWI master writes two bytes followed by reading four bytes from the slave 34.
34 TWIS — I2C compatible two-wire interface slave with EasyDMA 34.
34 TWIS — I2C compatible two-wire interface slave with EasyDMA Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id B A Reset 0x00000000 Id RW Field 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Description Disabled 0 Disable shortcut Enabled 1 Enable shortcut 34.9.
34 TWIS — I2C compatible two-wire interface slave with EasyDMA Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id H G Reset 0x00000000 Id RW Field 0 F E 0 0 0 0 0 0 0 0000000 Value Id Value Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Description See EVENTS_ERROR E RW RXSTARTED Write '1' to Enable interrupt for RXSTARTED event See EVENTS_RXSTARTED F Set 1 Enable Disabled
34 TWIS — I2C compatible two-wire interface slave with EasyDMA Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id H G Reset 0x00000000 Id G RW Field 0 F E B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Description Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW WRITE Write '1' to Disable interrupt for WRITE event See EVENTS_WRITE H Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read:
34 TWIS — I2C compatible two-wire interface slave with EasyDMA Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id A A A A Reset 0x00000000 Id RW Field 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Enabled 9 Description Enable TWIS 34.9.8 PSEL.
34 TWIS — I2C compatible two-wire interface slave with EasyDMA Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id A A A A A A A A Reset 0x00000000 Id RW Field A R 0 Value Id 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value AMOUNT Description Number of bytes transferred in the last RXD transaction 34.9.13 TXD.
34 TWIS — I2C compatible two-wire interface slave with EasyDMA 34.9.
34 TWIS — I2C compatible two-wire interface slave with EasyDMA Symbol Description Min. tTWIS,SU_STO,100kbps TWI slave setup time from SCL high to STOP condition, 100 kbps 5200 tTWIS,SU_STO,400kbps TWI slave setup time from SCL high to STOP condition, 400 kbps 1300 tTWIS,BUF,100kbps TWI slave bus free time between STOP and START conditions, Typ. Max.
35 UARTE — Universal asynchronous receiver/ transmitter with EasyDMA 35 UARTE — Universal asynchronous receiver/ transmitter with EasyDMA The Universal asynchronous receiver/transmitter with EasyDMA (UARTE) offers fast, full-duplex, asynchronous serial communication with built-in flow control (CTS, RTS) support in hardware at a rate up to 1 Mbps, and EasyDMA data transfer from/to RAM.
35 UARTE — Universal asynchronous receiver/ transmitter with EasyDMA The .PTR and .MAXCNT registers are double-buffered. They can be updated and prepared for the next RX/ TX transmission immediately after having received the RXSTARTED/TXSTARTED event. The ENDRX/ENDTX event indicates that EasyDMA has finished accessing respectively the RX/TX buffer in RAM. 35.3 Transmission The first step of a DMA transmission is storing bytes in the transmit buffer and configuring EasyDMA.
35 UARTE — Universal asynchronous receiver/ transmitter with EasyDMA The RX buffer is located at the address specified in the RXD.PTR register. The RXD.PTR register is doublebuffered and it can be updated and prepared for the next STARTRX task immediately after the RXSTARTED event is generated. The size of the RX buffer is specified in the RXD.MAXCNT register and the UARTE will generate an ENDRX event when it has filled up the RX buffer, see Figure 95: UARTE reception on page 335.
35 UARTE — Universal asynchronous receiver/ transmitter with EasyDMA 5 6 6 7 1 2 7 8 8 9 9 10 10 11, 12, 13, 14 11 12 13 3 14 ENDRX 4 5 RXTO 3 4 ENDRX 2 3 ENDRX 1 2 RXSTARTED Lifeline RXD 1 RXSTARTED EasyDMA To make sure that all data in the RX FIFO is moved to the RX buffer, the RXD.MAXCNT register must be set to RXD.MAXCNT > 4, see Figure 96: UARTE reception with forced stop via STOPRX on page 336.
35 UARTE — Universal asynchronous receiver/ transmitter with EasyDMA The STOPTX and STOPRX tasks may not be always needed (the peripheral might already be stopped), but if STOPTX and/or STOPRX is sent, software shall wait until the TXSTOPPED and/or RXTO event is received in response, before disabling the peripheral through the ENABLE register. 35.
35 UARTE — Universal asynchronous receiver/ transmitter with EasyDMA Register Offset Description ERRORSRC 0x480 Error source ENABLE 0x500 Enable UART PSEL.RTS 0x508 Pin select for RTS signal PSEL.TXD 0x50C Pin select for TXD signal PSEL.CTS 0x510 Pin select for CTS signal PSEL.RXD 0x514 Pin select for RXD signal BAUDRATE 0x524 Baud rate. Accuracy depends on the HFCLK source selected. RXD.PTR 0x534 Data pointer RXD.MAXCNT 0x538 Maximum number of bytes in receive buffer RXD.
35 UARTE — Universal asynchronous receiver/ transmitter with EasyDMA Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id L Reset 0x00000000 Id E RW Field 0 J I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Description Disabled 0 Disable Enabled 1 Enable RW TXDRDY Enable or disable interrupt for TXDRDY event See EVENTS_TXDRDY F Disabled 0 Disable Enabled 1 Enable RW ENDTX Enable o
35 UARTE — Universal asynchronous receiver/ transmitter with EasyDMA Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id L Reset 0x00000000 Id RW Field 0 J I H G F E Value Id Value Description Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled See EVENTS_RXDRDY D RW ENDRX Write '1' to Enable interrupt for ENDRX event See EVENTS_ENDRX E Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW TXDRDY Wr
35 UARTE — Universal asynchronous receiver/ transmitter with EasyDMA Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id L Reset 0x00000000 Id RW Field A RW CTS 0 Value Id J I H G F E Value Description Write '1' to Disable interrupt for CTS event See EVENTS_CTS B Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW NCTS Write '1' to Disable interrupt for NCTS event See EVENTS_NCTS C Clear 1 Disable Disabled 0 R
35 UARTE — Universal asynchronous receiver/ transmitter with EasyDMA Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id L Reset 0x00000000 Id RW Field 0 J I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Description Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled See EVENTS_TXSTOPPED 35.10.
35 UARTE — Universal asynchronous receiver/ transmitter with EasyDMA Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id B A A A A A Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Id RW Field A RW PIN B RW CONNECT Value Id Value [0..31] Description Pin number Connection Disconnected 1 Disconnect Connected 0 Connect 35.10.8 PSEL.
35 UARTE — Universal asynchronous receiver/ transmitter with EasyDMA Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id Reset 0x04000000 Id RW Field A RW BAUDRATE 0 AA A A A A A A AAAA A A A A A A A A A A A A A A A A A A A A 0 0 0 0 1 0 0 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Description Baud1200 0x0004F000 1200 baud (actual rate: 1205) Baud2400 0x0009D000 2400 baud (actual rate: 2396) Baud4800 0x0013B000 4800 ba
35 UARTE — Universal asynchronous receiver/ transmitter with EasyDMA Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id Reset 0x00000000 Id RW Field A RW PTR AA A A A A A A AAAA A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Description Data pointer 35.10.16 TXD.
35 UARTE — Universal asynchronous receiver/ transmitter with EasyDMA Symbol tUARTE,START,LP Description Min. Typ. Max.
36 QDEC — Quadrature decoder 36 QDEC — Quadrature decoder The Quadrature decoder (QDEC) provides buffered decoding of quadrature-encoded sensor signals. It is suitable for mechanical and optical sensors. The sample period and accumulation are configurable to match application requirements. The QDEC provides the following: • • • • Decoding of digital waveform from off-chip quadrature encoder. Sample accumulation eliminating hard real-time requirements to be enforced on application.
36 QDEC — Quadrature decoder The QDEC decodes the output from the off-chip encoder by sampling the QDEC phase input pins (A and B) at a fixed rate as specified in the SAMPLEPER register. If the SAMPLEPER value needs to be changed, the QDEC shall be stopped using the STOP task. SAMPLEPER can be then changed upon receiving the STOPPED event, and QDEC can be restarted using the START task. Failing to do so may result in unpredictable behaviour.
36 QDEC — Quadrature decoder Note that when when the debounce filters are enabled, displacements reported by the QDEC peripheral are delayed by one SAMPLEPER period. 36.4 Accumulators The quadrature decoder contains two accumulator registers, ACC and ACCDBL, that accumulate respectively valid motion sample values and the number of detected invalid samples (double transitions). The ACC register will accumulate all valid values (1/-1) written to the SAMPLE register.
36 QDEC — Quadrature decoder ON mode. When the peripheral is disabled, the pins will behave as regular GPIOs, and use the configuration in their respective OUT bit field and PIN_CNF[n] register. To secure correct behavior in the QDEC, the pins used by the QDEC must be configured in the GPIO peripheral as described in Table 84: GPIO configuration before enabling peripheral on page 350 before enabling the QDEC.
36 QDEC — Quadrature decoder Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id G F E D C B A Reset 0x00000000 Id RW Field A RW REPORTRDY_READCLRACC 0 Value Id 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Description Shortcut between REPORTRDY event and READCLRACC task See EVENTS_REPORTRDY and TASKS_READCLRACC B Disabled 0 Disable shortcut Enabled 1 Enable shortcut RW SAMPLERDY_STOP Shortcut between SAMPLERDY event
36 QDEC — Quadrature decoder Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id E D C B A Reset 0x00000000 Id D RW Field 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Description Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW DBLRDY Write '1' to Enable interrupt for DBLRDY event See EVENTS_DBLRDY E Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW STOPPED Write '1' to Enabl
36 QDEC — Quadrature decoder Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id A Reset 0x00000000 Id RW Field A RW ENABLE 0 Value Id 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Description Enable or disable the quadrature decoder When enabled the decoder pins will be active. When disabled the quadrature decoder pins are not active and can be used as GPIO . Disabled 0 Disable Enabled 1 Enable 36.7.
36 QDEC — Quadrature decoder Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id Reset 0x00000000 Id RW Field 0 Value Id AA A A A A A A AAAA A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Description The value is a 2's complement value, and the sign gives the direction of the motion. The value '2' indicates a double transition. 36.7.
36 QDEC — Quadrature decoder Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id Reset 0x00000000 Id RW Field A R 0 Value Id ACCREAD AA A A A A A A AAAA A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Description [-1024..1023] Snapshot of the ACC register. The ACCREAD register is updated when the READCLRACC or RDCLRACC task is triggered 36.7.11 PSEL.
36 QDEC — Quadrature decoder Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id A Reset 0x00000000 Id RW Field A RW DBFEN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Description Disabled 0 Debounce input filters disabled Enabled 1 Debounce input filters enabled Enable input debounce filters 36.7.
37 SAADC — Successive approximation analogto-digital converter 37 SAADC — Successive approximation analog-todigital converter The ADC is a differential successive approximation register (SAR) analog-to-digital converter.
37 SAADC — Successive approximation analogto-digital converter PSEL_A PSEL_A PSEL_A PSEL_A PSEL_A PSEL_A CH[X].CONFIG PSEL_A PSEL_A PSEL_A PSEL_A PSEL_A PSEL_A CH[X].PSELP NC AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 VDD NC AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 VDD ADC RAM MUX RESULT P RESP RESULT SAR core GAIN RESULT EasyDMA RESULT RESULT RESULT N RESN RESULT RESULT MUX RESULT.PTR START SAMPLE VDD Internal reference REFSEL STARTED END STOPPED STOP CH[X].
37 SAADC — Successive approximation analogto-digital converter The ADC has a wide selection of gains controlled in the GAIN field of the CH[n].CONFIG register. If CH[n].CONFIG.REFSEL=0, the input range of the ADC core is nominally ±0.6 V differential and the input must be scaled accordingly. The ADC has a temperature dependent offset.
37 SAADC — Successive approximation analogto-digital converter The SAMPLERATE register can be used as a local timer instead of triggering individual SAMPLE tasks. When SAMPLERATE.MODE is set to Timers, it is sufficient to trigger SAMPLE task only once in order to start the SAADC and triggering the STOP task will stop sampling. The SAMPLERATE.CC field controls the sample rate. The SAMPLERATE timer mode cannot be combined with SCAN mode, and only one channel can be enabled in this mode.
37 SAADC — Successive approximation analogto-digital converter 31 16 15 0 RESULT.PTR CH[2] 1st result CH[1] 1st result RESULT.PTR + 4 CH[1] 2nd result CH[5] 1st result RESULT.PTR + 8 CH[5] 2nd result CH[2] 2nd result (…) RESULT.PTR + 2*(RESULT.MAXCNT – 2) CH[5] last result CH[2] last result Figure 99: Example of RAM placement (even RESULT.MAXCNT), channels 1, 2 and 5 enabled Figure 100: Example of RAM placement (odd RESULT.
37 SAADC — Successive approximation analogto-digital converter Data RAM Result 0 Result 1 Result 2 Result 3 0 Sample and convert RAM 0x20000002 0x20000010 0x20000012 0x20000020 0x20000022 Sample and convert RAM END END Sample and convert RAM START SAMPLE SAMPLE RESULT.PTR = 0x20000020 START SAMPLE 3 SAMPLE 2 RESULT.MAX CNT START END_START = 1 RESULT.PTR = 0x20000000 1 RESULT.
37 SAADC — Successive approximation analogto-digital converter RESP = Pullup R Output Input R RESP = Pulldown Figure 102: Resistor ladder for positive input (negative input is equivalent, using RESN instead of RESP) 37.8 Reference The ADC can use two different references, controlled in the REFSEL field of the CH[n].CONFIG register. These are: • • Internal reference VDD as reference The internal reference results in an input range of ±0.6 V on the ADC core.
37 SAADC — Successive approximation analogto-digital converter ADC Rsource TACQ Figure 103: Simplified ADC sample network Table 88: Acquisition time TACQ [µs] 3 5 10 15 20 40 Maximum source resistance [kOhm] 10 40 100 200 400 800 37.10 Limits event monitoring A channel can be event monitored by configuring limit register CH[n].LIMIT. If the conversion result is higher than the defined high limit, or lower than the defined low limit, the appropriate event will get fired. VIN CH[n].LIMIT.HIGH CH[n].
37 SAADC — Successive approximation analogto-digital converter outside of the defined limits. It is not possible to fire an event when the input signal is inside a defined range by swapping high and low limits. The comparison to limits always takes place, there is no need to enable it. If comparison is not required on a channel, the software shall simply ignore the related events. In that situation, the value of the limits registers is irrelevant, so it does not matter if CH[n].LIMIT.
37 SAADC — Successive approximation analogto-digital converter Register Offset Description CH[2].PSELN 0x534 Input negative pin selection for CH[2] CH[2].CONFIG 0x538 Input configuration for CH[2] CH[2].LIMIT 0x53C High/low limits for event monitoring a channel CH[3].PSELP 0x540 Input positive pin selection for CH[3] CH[3].PSELN 0x544 Input negative pin selection for CH[3] CH[3].CONFIG 0x548 Input configuration for CH[3] CH[3].
37 SAADC — Successive approximation analogto-digital converter Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id V U T S R Q P O N M L K J Reset 0x00000000 Id RW Field E RW CALIBRATEDONE 0 Value Id Value Description Enable or disable interrupt for CALIBRATEDONE event See EVENTS_CALIBRATEDONE F Disabled 0 Disable Enabled 1 Enable RW STOPPED Enable or disable interrupt for STOPPED event See EVENTS_STOPPED G Disabled 0 Disable Enabled
37 SAADC — Successive approximation analogto-digital converter Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id V U T S R Q P O N M L K J Reset 0x00000000 Id R RW Field 0 I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Description Disabled 0 Disable Enabled 1 Enable RW CH5LIMITL Enable or disable interrupt for CH[5].LIMITL event See EVENTS_CH[5].
37 SAADC — Successive approximation analogto-digital converter Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id V U T S R Q P O N M L K J Reset 0x00000000 Id RW Field E RW CALIBRATEDONE 0 Value Id I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Description Write '1' to Enable interrupt for CALIBRATEDONE event See EVENTS_CALIBRATEDONE F Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled
37 SAADC — Successive approximation analogto-digital converter Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id V U T S R Q P O N M L K J Reset 0x00000000 Id RW Field 0 I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Description Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled See EVENTS_CH[4].LIMITH P RW CH4LIMITL Write '1' to Enable interrupt for CH[4].
37 SAADC — Successive approximation analogto-digital converter Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id V U T S R Q P O N M L K J Reset 0x00000000 Id B RW Field 0 I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Description Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW END Write '1' to Disable interrupt for END event See EVENTS_END C Clear 1 Disable Disabled 0 Read: Dis
37 SAADC — Successive approximation analogto-digital converter Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id V U T S R Q P O N M L K J Reset 0x00000000 Id RW Field L RW CH2LIMITL 0 I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Description Enabled 1 Read: Enabled Write '1' to Disable interrupt for CH[2].LIMITL event See EVENTS_CH[2].
37 SAADC — Successive approximation analogto-digital converter Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 Id V U T S R Q P O N M L K J Reset 0x00000000 Id RW Field V RW CH7LIMITL 0 Value Id 7 6 5 4 3 2 1 0 I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Description Write '1' to Disable interrupt for CH[7].LIMITL event See EVENTS_CH[7].
37 SAADC — Successive approximation analogto-digital converter 37.11.7 CH[0].
37 SAADC — Successive approximation analogto-digital converter Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id G Reset 0x00020000 Id RW Field F RW MODE 0 F E E E D C C C B B A A 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Description 40us 5 40 us SE 0 Diff 1 Disabled 0 Burst mode is disabled (normal operation) Enabled 1 Burst mode is enabled.
37 SAADC — Successive approximation analogto-digital converter Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id A A A A A Reset 0x00000000 Id RW Field 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Description AnalogInput1 2 AIN1 AnalogInput2 3 AIN2 AnalogInput3 4 AIN3 AnalogInput4 5 AIN4 AnalogInput5 6 AIN5 AnalogInput6 7 AIN6 AnalogInput7 8 AIN7 VDD 9 VDD 37.11.12 CH[1].
37 SAADC — Successive approximation analogto-digital converter Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id G Reset 0x00020000 Id RW Field 0 F E E E D C C C B B A A 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Enabled 1 Description Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. 37.11.13 CH[1].
37 SAADC — Successive approximation analogto-digital converter Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id A A A A A Reset 0x00000000 Id RW Field 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value VDD 9 Description VDD 37.11.16 CH[2].
37 SAADC — Successive approximation analogto-digital converter Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id B B B B B B B B BBBB B B B B A A A A A A A A A A A A A A A A Reset 0x7FFF8000 0 1 1 1 1 1 1 1 1111 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Id RW Field A B Value Id Value Description RW LOW [-32768 to +32767] Low level limit RW HIGH [-32768 to +32767] High level limit 37.11.18 CH[3].
37 SAADC — Successive approximation analogto-digital converter Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id G Reset 0x00020000 Id B C D E RW Field 0 F E E E D C C C B B A A 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Description Bypass 0 Bypass resistor ladder Pulldown 1 Pull-down to GND Pullup 2 Pull-up to VDD VDD1_2 3 Set input at VDD/2 Bypass 0 Bypass resistor ladder Pulldown 1 P
37 SAADC — Successive approximation analogto-digital converter Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id A A A A A Reset 0x00000000 Id RW Field A RW PSELP 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Description NC 0 Not connected AnalogInput0 1 AIN0 AnalogInput1 2 AIN1 AnalogInput2 3 AIN2 AnalogInput3 4 AIN3 AnalogInput4 5 AIN4 AnalogInput5 6 AIN5 AnalogInput6 7 AIN6 AnalogInput
37 SAADC — Successive approximation analogto-digital converter Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id G Reset 0x00020000 Id D E RW Field 0 F E E E D C C C B B A A 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Description Gain1_4 2 1/4 Gain1_3 3 1/3 Gain1_2 4 1/2 Gain1 5 1 Gain2 6 2 Gain4 7 4 Internal 0 Internal reference (0.
37 SAADC — Successive approximation analogto-digital converter Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id A A A A A Reset 0x00000000 Id RW Field 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Description AnalogInput6 7 AIN6 AnalogInput7 8 AIN7 VDD 9 VDD 37.11.27 CH[5].
37 SAADC — Successive approximation analogto-digital converter Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id G Reset 0x00020000 Id E RW Field 0 F E E E D C C C B B A A 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Description VDD1_4 1 VDD/4 as reference RW TACQ Acquisition time, the time the ADC uses to sample the input voltage F 3us 0 3 us 5us 1 5 us 10us 2 10 us 15us 3 15 us 20us 4 20
37 SAADC — Successive approximation analogto-digital converter Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id A A A A A Reset 0x00000000 Id RW Field A RW PSELN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Description NC 0 Not connected AnalogInput0 1 AIN0 AnalogInput1 2 AIN1 AnalogInput2 3 AIN2 AnalogInput3 4 AIN3 AnalogInput4 5 AIN4 AnalogInput5 6 AIN5 AnalogInput6 7 AIN6 AnalogInput
37 SAADC — Successive approximation analogto-digital converter Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id G Reset 0x00020000 Id RW Field G RW BURST 0 Value Id F E E E D C C C B B A A 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Description Enable burst mode Disabled 0 Burst mode is disabled (normal operation) Enabled 1 Burst mode is enabled.
37 SAADC — Successive approximation analogto-digital converter Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id A A A A A Reset 0x00000000 Id RW Field 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Description AnalogInput6 7 AIN6 AnalogInput7 8 AIN7 VDD 9 VDD 37.11.36 CH[7].
37 SAADC — Successive approximation analogto-digital converter High/low limits for event monitoring a channel Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id B B B B B B B B BBBB B B B B A A A A A A A A A A A A A A A A Reset 0x7FFF8000 0 1 1 1 1 1 1 1 1111 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Id RW Field A B Value Id Value Description RW LOW [-32768 to +32767] Low level limit RW HIGH [-32768 to +32767] High level limit 37.11.
37 SAADC — Successive approximation analogto-digital converter 37.11.41 RESULT.PTR Address offset: 0x62C Data pointer Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id Reset 0x00000000 Id RW Field A RW PTR AA A A A A A A AAAA A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Description Data pointer 37.11.42 RESULT.
37 SAADC — Successive approximation analogto-digital converter Symbol Description Min. Max. Units EG1/6 Errorb for Gain = 1/6 -3 Typ. 3 % EG1/4 Errorb for Gain = 1/4 -3 3 % EG1/2 Errorb for Gain = 1/2 -3 4 % EG1 Errorb for Gain = 1 -3 4 % CSAMPLE Sample and hold capacitance at maximum gain34 2.
DNL [LSB10b] 37 SAADC — Successive approximation analogto-digital converter 2 1.5 1 0.5 0 -0.5 -1 -1.5 -2 0 64 128 192 256 320 384 448 512 576 640 704 768 832 896 960 Output code Figure 107: ADC DNL vs Output Code 0 12-bit resolution Differential mode Internal reference 200kHz sampling frequency 3µs aquisition time 4096 point FFT (EasyDMA) SNDR = 56.6 dB ENOB = 9.
38 COMP — Comparator 38 COMP — Comparator The Comparator (COMP) compares the input voltage (VIN+) that is derived from an analog input pin selected via the PSEL register against a second input voltage (VIN-) that can be derived from multiple sources depending on operation mode.
38 COMP — Comparator to use and the output of the COMP is correct. When the COMP module is started, events will be generated every time VIN+ crosses VIN-. VIN- can be derived directly from AIN0 or AIN1 in differential mode, or VREF in single-ended mode. VUP and VDOWN thresholds can be set to implement a hysteresis on VIN- using the Reference Ladder. VREF can be derived from VDD, AIN0, AIN1 or internal 1.2V, 1.8V and 2.4V references.
38 COMP — Comparator MUX PSEL EXTREFSEL MUX SAMPLE STOP START ISOURCE AIN1 AIN0 AIN7 AIN6 AIN5 AIN4 AIN3 AIN2 AIN1 AIN0 Restriction: Depending on the device, not all the analog inputs may be available for each MUX.
MUX PSEL VIN+ + - VIN- EXTREFSEL MUX VDD VUP 0 AREF MUX VDOWN 1 Comparator core MODE REFSEL SAMPLE STOP START ISOURCE TH AIN1 AIN0 AIN7 AIN6 AIN5 AIN4 AIN3 AIN2 AIN1 AIN0 38 COMP — Comparator HYST RESULT Reference ladder VREF MUX 1V2 1V8 2V4 Output 0 = BELOW (VIN+ < VIN-) 1 = ABOVE (VIN+ > VIN-) READY DOWN UP CROSS Figure 112: Comparator in single-ended mode VIN+ VUP VDOWN Output ABOVE (VIN+ > VIN-) BELOW VUP VDOWN VUP RESULT BELOW ( VIN+ < VIN-) VIN- t
38 COMP — Comparator VIN+ VUP VDOWN Output BELOW ( VIN+ < VIN-) ABOVE (VIN+ > VIN-) BELOW VDOWN VUP VDOWN VUP BELOW 3 SAMPLE SAMPLE 2 START CPU 1 ABOVE UP DOWN READY ABOVE DOWN RESULT ABOVE (VIN+ > VIN-) VIN- t Figure 114: Hysteresis example where VIN+ starts above VUP 38.4 Pin configuration The user can use the PSEL register to select one of the analog input pins, AIN0 through AIN7, as input VIN +. See Figure 112: Comparator in single-ended mode on page 395.
38 COMP — Comparator Register Offset Description INTENCLR 0x308 Disable interrupt RESULT 0x400 Compare result ENABLE 0x500 COMP enable PSEL 0x504 Pin select REFSEL 0x508 Reference source select EXTREFSEL 0x50C External reference select TH 0x530 Threshold configuration for hysteresis unit MODE 0x534 Mode configuration HYST 0x538 Comparator hysteresis enable ISOURCE 0x53C Current source select on analog input 38.5.
38 COMP — Comparator Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id D C B A Reset 0x00000000 Id RW Field C 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Description Disabled 0 Disable Enabled 1 Enable RW UP Enable or disable interrupt for UP event See EVENTS_UP D Disabled 0 Disable Enabled 1 Enable RW CROSS Enable or disable interrupt for CROSS event See EVENTS_CROSS Disabled 0 Disable Enabl
38 COMP — Comparator Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id D C B A Reset 0x00000000 Id B RW Field 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Description Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW DOWN Write '1' to Disable interrupt for DOWN event See EVENTS_DOWN C Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW UP Write '1' to Disable interrupt for
38 COMP — Comparator Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id A A A Reset 0x00000000 Id RW Field 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Description AnalogInput0 0 AIN0 selected as analog input AnalogInput1 1 AIN1 selected as analog input AnalogInput2 2 AIN2 selected as analog input AnalogInput3 3 AIN3 selected as analog input AnalogInput4 4 AIN4 selected as analog input AnalogInput5
38 COMP — Comparator Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id B Reset 0x00000000 Id RW Field A RW SP B 0 A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Description Low 0 Low power mode Normal 1 Normal mode High 2 High speed mode SE 0 Single ended mode Diff 1 Differential mode Speed and power mode RW MAIN Main operation mode 38.5.
38 COMP — Comparator Symbol Description VDIFFHYST Optional hysteresis applied to differential input Min. VVDD-VREF Required difference between VDD and a selected VREF, VDD > Typ. Max. 30 Units mV 0.
39 LPCOMP — Low power comparator 39 LPCOMP — Low power comparator LPCOMP compares an input voltage against a reference voltage.
39 LPCOMP — Low power comparator hysteresis is enabled, the upward crossing level becomes (VIN- + VHYST/2), and the downward crossing level becomes (VIN- - VHYST/2). The LPCOMP is stopped by triggering the STOP task.
39 LPCOMP — Low power comparator 39.
39 LPCOMP — Low power comparator Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id E D C B A Reset 0x00000000 Id RW Field 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Enabled 1 Description Enable shortcut 39.3.
39 LPCOMP — Low power comparator Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id D C B A Reset 0x00000000 Id D RW Field 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Description Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW CROSS Write '1' to Disable interrupt for CROSS event See EVENTS_CROSS Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled 39.3.
39 LPCOMP — Low power comparator 39.3.
39 LPCOMP — Low power comparator Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id A Reset 0x00000000 Id RW Field A RW HYST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Description NoHyst 0 Comparator hysteresis disabled Hyst50mV 1 Comparator hysteresis disabled (typ. 50 mV) Comparator hysteresis enable 39.4 Electrical specification 39.4.
40 WDT — Watchdog timer 40 WDT — Watchdog timer A countdown watchdog timer using the low-frequency clock source (LFCLK) offers configurable and robust protection against application lock-up. The watchdog timer is started by triggering the START task. The watchdog can be paused during long CPU sleep periods for low power applications and when the debugger has halted the CPU. The watchdog is implemented as a down-counter that generates a TIMEOUT event when it wraps over after counting down to 0.
40 WDT — Watchdog timer 40.
40 WDT — Watchdog timer 40.4.3 RUNSTATUS Address offset: 0x400 Run status Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id A Reset 0x00000000 Id RW Field A R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Description NotRunning 0 Watchdog not running Running 1 Watchdog is running RUNSTATUS Indicates whether or not the watchdog is running 40.4.
40 WDT — Watchdog timer 40.4.
40 WDT — Watchdog timer Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id Reset 0x00000000 Id RW Field A W 0 AA A A A A A A AAAA A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Description Reload 0x6E524635 RR Reload request register Value to request a reload of the watchdog timer 40.4.
40 WDT — Watchdog timer Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id Reset 0x00000000 Id RW Field A W 0 AA A A A A A A AAAA A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Description Reload 0x6E524635 RR Reload request register Value to request a reload of the watchdog timer 40.4.
41 SWI — Software interrupts 41 SWI — Software interrupts A set of interrupts have been reserved for use as software interrupts. 41.
42 NFCT — Near field communication tag 42 NFCT — Near field communication tag The NFCT peripheral (referred to as the 'NFC peripheral' from now on) supports communication signal interface type A and 106 kbps bit rate from the NFC Forum. With appropriate software, the NFC peripheral can be used to emulate the listening device NFC-A as specified by the NFC Forum. Listed here are the main features for the NFC peripheral: • NFC-A listen mode operation • • • • • 13.
42 NFCT — Near field communication tag Wake-on-field is supported in SENSE mode while the device is either in System OFF or System ON mode. When the antenna enters an NFC field, an event will be triggered notifying the system to activate the NFC functionality for incoming frames. In System ON, if the energy detected at the antenna increases beyond a threshold value, the module will generate a FIELDDETECTED event.
42 NFCT — Near field communication tag Activated NFC (OTHER) (See activity) /COLLISION GOIDLE DISABLE DISABLE ACTIVATE IDLERU / READY NFC (ALL_REQ) / AUTOCOLRESSTARTED IDLE /SELECTED READY_A NFC (SENS_REQ) / AUTOCOLRESSTARTED NFC (ALL_REQ) / AUTOCOLRESSTARTED DISABLE SLEEP_A SENSE NFC (SLP_REQ) GOSLEEP ACTIVE_A ENABLERXDATA SENSE_FIELD STARTTX SENSE RECEIVE STARTTX TRANSMIT /TXFRAMEEND ACTIVATE /RXFRAMEEND / RXERROR Figure 118: NFC state diagram 42.
42 NFCT — Near field communication tag RXFRAMEND event for the respective ongoing transmit or receive before starting a new receive or transmit operation. The MAXLEN register determines the maximum number of bytes that can be read from or written to the RAM. This feature can be used to secure that the NFC peripheral does not overwrite, or read beyond, the RAM assigned to a packet. Note that if the RXD.AMOUNT or TXD.
42 NFCT — Near field communication tag The hardware implementation can handle the states from IDLE to ACTIVE_A automatically as defined in the NFC Forum, NFC Activity Technical Specification, and the other states are to be handled by software. The software keeps track of the state through events. The collision resolution will trigger an AUTOCOLRESSTARTED event when it has started. Reaching the ACTIVE_A state is indicated by the SELECTED event. If collision resolution fails, a COLLISION event is triggered.
42 NFCT — Near field communication tag Receive Last data bit Transmit EoF Subcarrier continues in the 3 cases below Logic ‘0’ Logic ‘1’ FRAMEDELAYMAX 20/f c 84/f c Before Min FRAMEDELAYMIN STARTTX task SoF Subcarrier modulation Between Min and Max STARTTX task SoF Subcarrier modulation After Max (or missing) STARTTX task Subcarrier modulation ERROR event Figure 119: Frame timing controller (FRAMEDELAYMODE=Window) 42.
42 NFCT — Near field communication tag The Frame Assemble operation is illustrated in Figure 120: Frame assemble on page 423 for different settings in TXD.FRAMECONFIG. All shaded bits fields are added by the frame assembler. Some of these bits are optional and appearances are configured in TXD.FRAMECONFIG. Please note that the frames illustrated do not necessarily comply with the NFC specification. The figure is only to illustrate the behavior of the NFC peripheral.
42 NFCT — Near field communication tag 42.8 Antenna interface In ACTIVATED state, an amplitude regulator will adjust the voltage swing on the antenna pins to a value that is within the Vswing limit. Refer to NFCT Electrical Specification on page 436. 42.9 NFCT antenna recommendations The NFCT antenna coil must be connected differential between NFC1 and NFC2 pins of the device. Two external capacitors should be used to tune the resonance of the antenna circuit to 13.56 MHz.
42 NFCT — Near field communication tag 42.11 References NFC Forum, NFC Analog Specification version 1.0, www.nfc-forum.org NFC Forum, NFC Digital Protocol Technical Specification version 1.1, www.nfc-forum.org NFC Forum, NFC Activity Technical Specification version 1.1, www.nfc-forum.org 42.
42 NFCT — Near field communication tag Register Offset Description RXD.AMOUNT 0x524 Size of last incoming frame NFCID1_LAST 0x590 Last NFCID1 part (4, 7 or 10 bytes ID) NFCID1_2ND_LAST 0x594 Second last NFCID1 part (7 or 10 bytes ID) NFCID1_3RD_LAST 0x598 Third last NFCID1 part (10 bytes ID) SENSRES 0x5A0 NFC-A SENS_RES auto-response settings SELRES 0x5A4 NFC-A SEL_RES auto-response settings 42.12.
42 NFCT — Near field communication tag Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id TSR Reset 0x00000000 Id RW Field 0 0 0 0 0 0 0 0 000000000 Value Id Value Disabled 0 Disable Enabled 1 Enable N M L K H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Description See EVENTS_RXFRAMESTART G RW RXFRAMEEND Enable or disable interrupt for RXFRAMEEND event See EVENTS_RXFRAMEEND H Disabled 0 Disable Enabled 1 Enable RW ERROR Enabl
42 NFCT — Near field communication tag Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id T S R Reset 0x00000000 Id B RW Field 0 N M L K H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Description Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW FIELDDETECTED Write '1' to Enable interrupt for FIELDDETECTED event See EVENTS_FIELDDETECTED C Set 1 Enable Disabled 0 Rea
42 NFCT — Near field communication tag Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id T S R Reset 0x00000000 Id N RW Field 0 N M L K H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Description Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW AUTOCOLRESSTARTED Write '1' to Enable interrupt for AUTOCOLRESSTARTED event See EVENTS_AUTOCOLRESSTARTED R Set 1 Enable Disabled 0 Read: D
42 NFCT — Near field communication tag Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id T S R Reset 0x00000000 Id RW Field E RW TXFRAMEEND 0 Value Id N M L K H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Description Write '1' to Disable interrupt for TXFRAMEEND event See EVENTS_TXFRAMEEND F Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW RXFRAMESTART Write '1' to Disable i
42 NFCT — Near field communication tag Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id T S R Reset 0x00000000 Id RW Field 0 N M L K H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Description Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled See EVENTS_STARTED 42.12.5 ERRORSTATUS Address offset: 0x404 NFC Error Status register Write a bit to '1' to clear it.
42 NFCT — Near field communication tag Indicates the presence or not of a valid field Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id B A Reset 0x00000000 Id RW Field A R 0 Value Id 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Description FIELDPRESENT Indicates the presence or not of a valid field. Available only in the activated state.
42 NFCT — Near field communication tag Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id Reset 0x00000000 Id RW Field A RW PTR 0 Value Id AA A A A A A A AAAA A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Description Packet pointer for TXD and RXD data storage in Data RAM. Thisaddress is a byte aligned RAM address. 42.12.
42 NFCT — Near field communication tag 42.12.16 RXD.
42 NFCT — Near field communication tag Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id C C C C C C C C B B B B B B B B A A A A A A A A Reset 0x00000000 0 Value Id 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Id RW Field Value Description A RW NFCID1_V NFCID1 byte V B RW NFCID1_U NFCID1 byte U C RW NFCID1_T NFCID1 byte T 42.12.
42 NFCT — Near field communication tag Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id E D D C C B A A Reset 0x00000000 Id RW Field A RW RFU10 B RW CASCADE 0 Value Id 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Description Reserved for future use. Shall be 0.
43 PDM — Pulse density modulation interface 43 PDM — Pulse density modulation interface The pulse density modulation (PDM) module enables input of pulse density modulated signals from external audio frontends, for example, digital microphones. The PDM module generates the PDM clock and supports single-channel or dual-channel (Left and Right) data input. Data is transferred directly to RAM buffers using EasyDMA.
43 PDM — Pulse density modulation interface The continuous transfer can be started or stopped by sending the START and STOP tasks. STOP becomes effective after the current frame has finished transferring, which will generate the STOPPED event. The STOPPED event indicates that all activity in the module are finished, and that the data is available in RAM (EasyDMA has finished transferring as well). Attempting to restart before receiving the STOPPED event may result in unpredictable behaviour. 43.
43 PDM — Pulse density modulation interface For a given value of SAMPLE.MAXCNT, the buffer in RAM can contain half the stereo sampling time as compared to the mono sampling time. The PDM acquisition can be started by the START task, after the SAMPLE.PTR and SAMPLE.MAXCNT registers have been written. When starting the module, it will take some time for the filters to start outputting valid data. Transients from the PDM microphone itself may also occur.
43 PDM — Pulse density modulation interface The PSEL.CLK and PSEL.DIN registers and their configurations are only used as long as the PDM module is enabled, and retained only as long as the device is in System ON mode. See POWER — Power supply on page 78 for more information about power modes. When the peripheral is disabled, the pins will behave as regular GPIOs, and use the configuration in their respective OUT bit field and PIN_CNF[n] register.
43 PDM — Pulse density modulation interface Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id C B A Reset 0x00000000 Id RW Field A RW STARTED 0 Value Id 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Description Enable or disable interrupt for STARTED event See EVENTS_STARTED B Disabled 0 Disable Enabled 1 Enable RW STOPPED Enable or disable interrupt for STOPPED event See EVENTS_STOPPED C Disabled 0 Disable Ena
43 PDM — Pulse density modulation interface Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id C B A Reset 0x00000000 Id RW Field 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Description Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled See EVENTS_STOPPED C RW END Write '1' to Disable interrupt for END event See EVENTS_END Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read
43 PDM — Pulse density modulation interface 43.7.7 GAINL Address offset: 0x518 Left output gain adjustment Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id A A A A A A A Reset 0x00000028 Id RW Field A RW GAINL 0 Value Id 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 Value Description Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.
43 PDM — Pulse density modulation interface Pin number configuration for PDM DIN signal Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id B A A A A A Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Id RW Field A RW PIN B RW CONNECT Value Id Value Description [0..31] Pin number Connection Disconnected 1 Disconnect Connected 0 Connect 43.7.11 SAMPLE.
43 PDM — Pulse density modulation interface tPDM,CLK CLK tPDM,cv tPDM,s DIN (L) tPDM,cv tPDM,s tPDM,h =tPDM,ci DIN(R) Figure 128: PDM timing diagram Page 445 tPDM,h =tPDM,ci
44 I2S — Inter-IC sound interface 44 I2S — Inter-IC sound interface The I2S (Inter-IC Sound) module, supports the original two-channel I2S format, and left or right-aligned formats. It implements EasyDMA for sample transfer directly to and from RAM without CPU intervention.
44 I2S — Inter-IC sound interface TX data is written to the SDOUT pin on the falling edge of SCK, and RX data is read from the SDIN pin on the rising edge of SCK. The most significant bit (MSB) is always transmitted first. TX and RX are available in both Master and Slave modes and can be enabled/disabled independently in the CONFIG.TXEN on page 456 and CONFIG.RXEN on page 456. Transmission and/or reception is started by triggering the START task. When started and transmission is enabled (in CONFIG.
44 I2S — Inter-IC sound interface When operating in Master mode the SCK is generated from the MCK, and the frequency of SCK is then given as: SCK = 2 * LRCK * CONFIG.SWIDTH The falling edge of the SCK falls on the toggling edge of LRCK. When operating in Slave mode SCK is provided by the external I2S master. 44.5 Master clock (MCK) The master clock (MCK) is the clock from which LRCK and SCK are derived when operating in Master mode. The MCK is generated by an internal MCK generator.
44 I2S — Inter-IC sound interface When using I2S format, the first bit in a half-frame (containing one left or right sample) gets sampled on the second rising edge of the SCK after a LRCK edge. When using Aligned mode, the first bit in a half-frame gets sampled on the first rising edge of SCK following a LRCK edge. For data being received on SDIN the sample value can be either right or left-aligned inside a half-frame, as specified in CONFIG.ALIGN on page 458. CONFIG.
44 I2S — Inter-IC sound interface 44.7 EasyDMA The I2S module implements EasyDMA for accessing internal Data RAM without CPU intervention. The source and destination pointers for the TX and RX data are configured in TXD.PTR on page 459 and RXD.PTR on page 459. The memory pointed to by these pointers will only be read or written when TX or RX are enabled in CONFIG.TXEN on page 456 and CONFIG.RXEN on page 456. The addresses written to the pointer registers TXD.PTR on page 459 and RXD.
44 I2S — Inter-IC sound interface 31 24 23 16 15 8 7 0 x.PTR Left sample 3 Left sample 2 Left sample 1 Left sample 0 x.PTR + 4 Left sample 7 Left sample 6 Left sample 5 Left sample 4 Left sample n-1 Left sample n-2 Left sample n-3 Left sample n-4 x.PTR + n - 4 Figure 135: Memory mapping for 8 bit mono. CONFIG.SWIDTH = 8Bit, CONFIG.CHANNELS = Left. 31 16 15 0 x.PTR Right sample 0 Left sample 0 x.PTR + 4 Right sample 1 Left sample 1 Right sample n - 1 Left sample n - 1 x.
44 I2S — Inter-IC sound interface 31 23 0 x.PTR Sign ext. Left sample 0 x.PTR + 4 Sign ext. Left sample 1 Sign ext. Left sample n - 1 x.PTR + (n*4) - 4 Figure 139: Memory mapping for 24 bit mono, left channel only. CONFIG.SWIDTH = 24Bit, CONFIG.CHANNELS = Left. 44.8 Module operation Described here is a typical operating procedure for the I2S module. 1. Configure the I2S module using the CONFIG registers // Enable reception NRF_I2S->CONFIG.
44 I2S — Inter-IC sound interface I2S_PSEL_LRCK_CONNECT_Pos); // SDOUT routed to pin 3 NRF_I2S->PSEL.SDOUT = (3 << I2S_PSEL_SDOUT_PIN_Pos) | (I2S_PSEL_SDOUT_CONNECT_Connected << I2S_PSEL_SDOUT_CONNECT_Pos); // SDIN routed on pin 4 NRF_I2S->PSEL.SDIN = (4 << I2S_PSEL_SDIN_PIN_Pos) | (I2S_PSEL_SDIN_CONNECT_Connected << I2S_PSEL_SDIN_CONNECT_Pos); 3. Configure TX and RX data pointers using the TXD, RXD and RXTXD registers NRF_I2S->TXD.PTR = my_tx_buf; NRF_I2S->RXD.PTR = my_rx_buf; NRF_I2S->TXD.
44 I2S — Inter-IC sound interface I2S signal SCK SDIN SDOUT I2S pin As specified in PSEL.SCK As specified in PSEL.SDIN As specified in PSEL.SDOUT Direction Output Input Output Output value 0 Not applicable 0 Comment Table 107: GPIO configuration before enabling peripheral (slave mode) I2S signal MCK LRCK SCK SDIN SDOUT I2S pin As specified in PSEL.MCK As specified in PSEL.LRCK As specified in PSEL.SCK As specified in PSEL.SDIN As specified in PSEL.
44 I2S — Inter-IC sound interface Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id F Reset 0x00000000 Id RW Field B RW RXPTRUPD 0 Value Id C B 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Description Enable or disable interrupt for RXPTRUPD event See EVENTS_RXPTRUPD C Disabled 0 Disable Enabled 1 Enable RW STOPPED Enable or disable interrupt for STOPPED event See EVENTS_STOPPED F Disabled 0 Disable Enabled
44 I2S — Inter-IC sound interface Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id F Reset 0x00000000 Id RW Field 0 C B 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Description Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled See EVENTS_STOPPED F RW TXPTRUPD Write '1' to Disable interrupt for TXPTRUPD event See EVENTS_TXPTRUPD Clear 1 Disable Disabled 0 Read: Disabled Enabled 1
44 I2S — Inter-IC sound interface Transmission (TX) enable. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id A Reset 0x00000001 Id RW Field A RW TXEN 0 Value Id 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Value Description Transmission (TX) enable. Disabled 0 Transmission disabled and now data will be read from theRXD.TXD Enabled 1 Transmission enabled. address. 44.10.8 CONFIG.
44 I2S — Inter-IC sound interface Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id A A A A Reset 0x00000006 Id RW Field A RW RATIO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 Value Id Value Description 32X 0 LRCK = MCK / 32 48X 1 LRCK = MCK / 48 64X 2 LRCK = MCK / 64 96X 3 LRCK = MCK / 96 128X 4 LRCK = MCK / 128 192X 5 LRCK = MCK / 192 256X 6 LRCK = MCK / 256 384X 7 LRCK = MCK / 384 512X 8 LRCK = M
44 I2S — Inter-IC sound interface Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id A A Reset 0x00000000 Id RW Field A RW CHANNELS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Description Stereo 0 Stereo. Left 1 Left only. Right 2 Right only. Enable channels. 44.10.15 RXD.PTR Address offset: 0x538 Receive buffer RAM start address.
44 I2S — Inter-IC sound interface 44.10.19 PSEL.SCK Address offset: 0x564 Pin select for SCK signal. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id C A A A A A Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Id RW Field A RW PIN C RW CONNECT Value Id Value Description [0..31] Pin number Connection Disconnected 1 Disconnect Connected 0 Connect 44.10.20 PSEL.
44 I2S — Inter-IC sound interface 44.11 Electrical specification 44.11.1 I2S timing specification Symbol Description tS_SDIN SDIN setup time before SCK rising Min. tH_SDIN SDIN hold time after SCK rising tS_SDOUT SDOUT setup time after SCK falling tH_SDOUT SDOUT hold time before SCK falling tSCK_LRCK SCLK falling to LRCK edge fMCK MCK frequency fLRCK LRCK frequency fSCK SCK frequency DCCK Clock duty cycle (MCK, LRCK, SCK) 20 Typ. Max.
45 MWU — Memory watch unit 45 MWU — Memory watch unit The Memory watch unit (MWU) can be used to generate events when a memory region is accessed by the CPU. The MWU can be configured to trigger events for access to Data RAM and Peripheral memory segments. The MWU allows an application developer to generate memory access events during development for debugging or during production execution for failure detection and recovery.
45 MWU — Memory watch unit Table 112: Register Overview Register Offset Description EVENTS_REGION[0].WA 0x100 Write access to region 0 detected EVENTS_REGION[0].RA 0x104 Read access to region 0 detected EVENTS_REGION[1].WA 0x108 Write access to region 1 detected EVENTS_REGION[1].RA 0x10C Read access to region 1 detected EVENTS_REGION[2].WA 0x110 Write access to region 2 detected EVENTS_REGION[2].RA 0x114 Read access to region 2 detected EVENTS_REGION[3].
45 MWU — Memory watch unit Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id L K J Reset 0x00000000 Id RW Field B RW REGION0RA 0 I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Description Enabled 1 Enable Enable or disable interrupt for REGION[0].RA event See EVENTS_REGION[0].RA C Disabled 0 Disable Enabled 1 Enable RW REGION1WA Enable or disable interrupt for REGION[1].
45 MWU — Memory watch unit Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id L K J Reset 0x00000000 Id RW Field A RW REGION0WA 0 Value Id I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Description Write '1' to Enable interrupt for REGION[0].WA event See EVENTS_REGION[0].WA B Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW REGION0RA Write '1' to Enable interrupt for REGION[0].
45 MWU — Memory watch unit Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id L K J Reset 0x00000000 Id RW Field 0 I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Description Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled See EVENTS_PREGION[1].WA L RW PREGION1RA Write '1' to Enable interrupt for PREGION[1].RA event See EVENTS_PREGION[1].
45 MWU — Memory watch unit Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id L K J Reset 0x00000000 Id H RW Field 0 I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Description Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW REGION3RA Write '1' to Disable interrupt for REGION[3].RA event See EVENTS_REGION[3].
45 MWU — Memory watch unit Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 Id L K J Reset 0x00000000 Id RW Field D RW REGION1RA 0 Value Id I 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Description Enable or disable non-maskable interrupt for REGION[1].RA event See EVENTS_REGION[1].RA E Disabled 0 Disable Enabled 1 Enable RW REGION2WA Enable or disable non-maskable interrupt for REGION[2].WA event See EVENTS_REGION[2].
45 MWU — Memory watch unit Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id L K J Reset 0x00000000 Id RW Field A RW REGION0WA 0 Value Id I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Description Write '1' to Enable non-maskable interrupt for REGION[0].WA event See EVENTS_REGION[0].
45 MWU — Memory watch unit Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id L K J Reset 0x00000000 Id J RW Field 0 I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Description Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW PREGION0RA Write '1' to Enable non-maskable interrupt for PREGION[0].RA event See EVENTS_PREGION[0].
45 MWU — Memory watch unit Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id L K J Reset 0x00000000 Id E RW Field 0 I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Description Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW REGION2WA Write '1' to Disable non-maskable interrupt for REGION[2].WA event See EVENTS_REGION[2].
45 MWU — Memory watch unit 45.1.7 PERREGION[0].
45 MWU — Memory watch unit Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id f e d c b a Z Y XWVU T S R Q P O N M L K J Reset 0x00000000 0 0 0 0 0 0 0 0 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Id R S T U V W X Y Z a b c d e f RW Field Value Id Value Description NoAccess 0 No write access occurred in this subregion Access 1 Write access(es) occurred in this subregion NoAccess 0 No write access occurred in this sub
45 MWU — Memory watch unit Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id f e d c b a Z Y XWVU T S R Q P O N M L K J Reset 0x00000000 0 0 0 0 0 0 0 0 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Id RW Field A RW SR0 B C D E F G H I J K L M N O P Q R S Value Id Value Description NoAccess 0 No read access occurred in this subregion Access 1 Read access(es) occurred in this subregion NoAccess 0 No read access occ
45 MWU — Memory watch unit Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id f e d c b a Z Y XWVU T S R Q P O N M L K J Reset 0x00000000 0 0 0 0 0 0 0 0 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Id T U V W X Y Z a b c d e f RW Field Value Id Value Description NoAccess 0 No read access occurred in this subregion Access 1 Read access(es) occurred in this subregion NoAccess 0 No read access occurred in this subregion A
45 MWU — Memory watch unit Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id f e d c b a Z Y X W VUT S RQPO N ML K J Reset 0x00000000 0 0 0 0 0 0 0 0 00000000000000 0 0 0 0 0 0 0 0 0 0 Id RW Field B RW SR1 C D E F G H I J K L M N O P Q R S T Value Id Value Description NoAccess 0 No write access occurred in this subregion Access 1 Write access(es) occurred in this subregion NoAccess 0 No write access occurred in thi
45 MWU — Memory watch unit Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id f e d c b a Z Y X W VUT S RQPO N ML K J Reset 0x00000000 0 0 0 0 0 0 0 0 00000000000000 0 0 0 0 0 0 0 0 0 0 Id U V W X Y Z a b c d e f RW Field Value Id Value Description NoAccess 0 No write access occurred in this subregion Access 1 Write access(es) occurred in this subregion NoAccess 0 No write access occurred in this subregion Access 1 Write
45 MWU — Memory watch unit Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id f e d c b a Z Y XWVU T S R Q P O N M L K J Reset 0x00000000 0 0 0 0 0 0 0 0 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Id RW Field C RW SR2 D E F G H I J K L M N O P Q R S T U Value Id Value Description NoAccess 0 No read access occurred in this subregion Access 1 Read access(es) occurred in this subregion NoAccess 0 No read access occ
45 MWU — Memory watch unit Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id f e d c b a Z Y XWVU T S R Q P O N M L K J Reset 0x00000000 0 0 0 0 0 0 0 0 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Id V W X Y Z a b c d e f RW Field Value Id Value Description NoAccess 0 No read access occurred in this subregion Access 1 Read access(es) occurred in this subregion NoAccess 0 No read access occurred in this subregion Access
45 MWU — Memory watch unit Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id L K J Reset 0x00000000 Id E F G H I J K L RW Field 0 I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Description Disable 0 Disable read access watch in this region Enable 1 Enable read access watch in this region Disable 0 Disable write access watch in this region Enable 1 Enable write access watch in th
45 MWU — Memory watch unit Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id L K J Reset 0x00000000 Id RW Field F RW RGN2RA G H I J K L 0 I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Description Enabled 1 Write access watch in this region is enabled Set 1 Enable read access watch in this region Disabled 0 Read access watch in this region is disabled Enabled 1 Read access watch
45 MWU — Memory watch unit Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id L K J Reset 0x00000000 Id RW Field E RW RGN2WA F G H I J K L 0 I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Description Clear 1 Disable write access watch in this region Disabled 0 Write access watch in this region is disabled Enabled 1 Write access watch in this region is enabled Clear 1 Disable rea
45 MWU — Memory watch unit 45.1.16 REGION[1].START Address offset: 0x610 Start address for region 1 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id Reset 0x00000000 Id RW Field A RW START 0 Value Id AA A A A A A A AAAA A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Description Start address for region 45.1.17 REGION[1].
45 MWU — Memory watch unit Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id Reset 0x00000000 Id RW Field A RW END 0 Value Id AA A A A A A A AAAA A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Description End address of region. 45.1.22 PREGION[0].
45 MWU — Memory watch unit Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id f e d c b a Z Y X W VUT S RQPO N ML K J Reset 0x00000000 0 0 0 0 0 0 0 0 0000000000000 0 0 0 0 0 0 0 0 0 0 0 Id RW Field H RW SR7 I J K L M N O P Q R S T U V W X Y Z Value Id Value Description Exclude 0 Exclude Include 1 Include Exclude 0 Exclude Include 1 Include Exclude 0 Exclude Include 1 Include Exclude 0 Exclude Include
45 MWU — Memory watch unit Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id f e d c b a Z Y X W VU T S R Q P O N M L K J Reset 0x00000000 0 0 0 0 0 0 0 0 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Id a b c d e f RW Field Value Id Value Description Exclude 0 Exclude Include 1 Include Exclude 0 Exclude Include 1 Include Exclude 0 Exclude Include 1 Include Exclude 0 Exclude Include 1 Include Exclude 0 Exclude
45 MWU — Memory watch unit Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id f e d c b a Z Y XWVU T S R Q P O N M L K J Reset 0x00000000 0 0 0 0 0 0 0 0 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Id RW Field B RW SR1 C D E F G H I J K L M N O P Q R S Value Id Value Description Include 1 Include Exclude 0 Exclude Include 1 Include Exclude 0 Exclude Include 1 Include Exclude 0 Exclude Include 1 Include
45 MWU — Memory watch unit Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id f e d c b a Z Y X W VUT S RQPO N ML K J Reset 0x00000000 0 0 0 0 0 0 0 0 0000000000000 0 0 0 0 0 0 0 0 0 0 0 Id RW Field T RW SR19 U V W X Y Z a b c d e f Value Id Value Description Exclude 0 Exclude Include 1 Include Exclude 0 Exclude Include 1 Include Exclude 0 Exclude Include 1 Include Exclude 0 Exclude Include 1 Include Exclu
46 EGU — Event generator unit 46 EGU — Event generator unit The Event generator unit (EGU) provides support for inter-layer signaling. This means support for atomic triggering of both CPU execution and hardware tasks from both firmware (by CPU) and hardware (by PPI). This feature can, for instance, be used for triggering CPU execution at a lower priority execution from a higher priority execution, or to handle a peripheral's ISR execution at a lower priority for some of its events.
46 EGU — Event generator unit Register Offset Description EVENTS_TRIGGERED[5] 0x114 Event number 5 generated by triggering the corresponding TRIGGER[5] task EVENTS_TRIGGERED[6] 0x118 Event number 6 generated by triggering the corresponding TRIGGER[6] task EVENTS_TRIGGERED[7] 0x11C Event number 7 generated by triggering the corresponding TRIGGER[7] task EVENTS_TRIGGERED[8] 0x120 Event number 8 generated by triggering the corresponding TRIGGER[8] task EVENTS_TRIGGERED[9] 0x124 Event number 9 gene
46 EGU — Event generator unit Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id P O N M L K J Reset 0x00000000 Id I RW Field 0 I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Description Enabled 1 Enable RW TRIGGERED8 Enable or disable interrupt for TRIGGERED[8] event See EVENTS_TRIGGERED[8] J Disabled 0 Disable Enabled 1 Enable RW TRIGGERED9 Enable or disable interrupt for TRIGGERED[9]
46 EGU — Event generator unit Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id P O N M L K J Reset 0x00000000 Id C RW Field 0 I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Description Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW TRIGGERED2 Write '1' to Enable interrupt for TRIGGERED[2] event See EVENTS_TRIGGERED[2] D Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read:
46 EGU — Event generator unit Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id P O N M L K J Reset 0x00000000 Id M RW Field 0 I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Description Enabled 1 Read: Enabled RW TRIGGERED12 Write '1' to Enable interrupt for TRIGGERED[12] event See EVENTS_TRIGGERED[12] N Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW TRIGGERED13 W
46 EGU — Event generator unit Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id P O N M L K J Reset 0x00000000 Id RW Field 0 I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Description Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled See EVENTS_TRIGGERED[4] F RW TRIGGERED5 Write '1' to Disable interrupt for TRIGGERED[5] event See EVENTS_TRIGGERED[5] G Clear 1 Disable
46 EGU — Event generator unit Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id P O N M L K J Reset 0x00000000 Id P 0 RW Field I H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Description Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW TRIGGERED15 Write '1' to Disable interrupt for TRIGGERED[15] event See EVENTS_TRIGGERED[15] Clear 1 Disable Disabled 0 Read: Disab
47 PWM — Pulse width modulation 47 PWM — Pulse width modulation The PWM module enables the generation of pulse width modulated signals on GPIO. The module implements an up or up-and-down counter with four PWM channels that drive assigned GPIOs. Three PWM modules can provide up to 12 PWM channels with individual frequency control in groups of up to four channels. Furthermore, a built-in decoder and EasyDMA capabilities make it possible to manipulate the PWM duty cycles without CPU intervention.
47 PWM — Pulse width modulation and when loading a new value from RAM during a sequence playback. If DECODER.LOAD=WaveForm, the register value is ignored, and taken from RAM instead (see Decoder with EasyDMA on page 499 below). Figure 142: PWM up counter example - FallingEdge polarity on page 497 shows the counter operating in up (MODE=PWM_MODE_Up) mode with three PWM channels with the same frequency but different duty cycle.
47 PWM — Pulse width modulation Figure 143: PWM up-and-down counter example on page 498 shows the counter operating in up and down mode with (MODE=PWM_MODE_UpAndDown) two PWM channels with the same frequency but different duty cycle and output polarity. The counter starts decrementing to zero when COUNTERTOP is reached and will invert the OUT[n] when compare value is hit for the second time. This results in a set of pulses that are center- aligned.
47 PWM — Pulse width modulation 47.2 Decoder with EasyDMA The decoder uses EasyDMA to take PWM parameters stored in Data RAM by ways of EasyDMA and updates the internal compare registers of the wave counter based on the mode of operation. The mentioned PWM parameters are organized into a sequence containing at least one half word (16 bit). Its most significant bit[15] denotes the polarity of the OUT[n] while bit[14:0] is the 15-bit compare value.
47 PWM — Pulse width modulation SEQ[n].PTR is the pointer used to fetch COMPARE values from RAM. If the SEQ[n].PTR is not pointing to the Data RAM region, an EasyDMA transfer may result in a HardFault or RAM corruption. See Memory on page 23 for more information about the different memory regions. After the SEQ[n].PTR is set to the desired RAM location, the SEQ[n].CNT register must be set to the number of 16-bit half words in the sequence.
47 PWM — Pulse width modulation Figure 145: Simple sequence example on page 501 depicts the source code used for configuration and timing details in a sequence where only sequence 0 is used and only run once with a new PWM duty cycle for each period. NRF_PWM0->PSEL.
47 PWM — Pulse width modulation NRF_PWM0->PSEL.
SEQ[0].CNT SEQ[0].ENDDELA Y EVENTS_SEQEND[0] SEQ[0].ENDDELA Y EVENTS_SEQSTARTED[1] EVENTS_SEQEND[1] SEQ[1].CNT SEQ[0].CNT EVENTS_SEQSTARTED[1] SEQ[1].CNT EVENTS_SEQEND[1] EVENTS_LOOPSDONE SEQ[1].ENDDELA Y 1 SEQ[0].ENDDELA Y SEQ[0].CNT EVENTS_SEQEND[0] SEQ[0].ENDDELA Y last loaded duty cycle maintained 47 PWM — Pulse width modulation EVENTS_SEQEND[0] TASKS_SEQSTART[0] EVENTS_SEQSTARTED[0] last loaded duty cycle maintained EVENTS_SEQSTARTED[0] (LOOP.CNT - 1) ... SEQ[0].
47 PWM — Pulse width modulation SEQ[1].ENDDELA Y SEQ[0].ENDDELA Y SEQ[0].CNT SEQ[1].CNT SEQ[0].ENDDELA Y SEQ[1].CNT 1 (LOOP.CNT - 1) ... SEQ[0].CNT SEQ[1].CNT SEQ[1].ENDDELA Y LOOP.
47 PWM — Pulse width modulation Table 117: Recommended GPIO configuration before starting PWM generation PWM signal OUT[n] PWM pin As specified in PSEL.OUT[n] (n=0..3) Direction Output Output value 0 Comment Idle state defined in GPIO->OUT 47.
47 PWM — Pulse width modulation 47.5.
47 PWM — Pulse width modulation Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id H G F E D C B Reset 0x00000000 Id RW Field 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Description Disabled 0 Disable Enabled 1 Enable See EVENTS_SEQEND[1] G RW PWMPERIODEND Enable or disable interrupt for PWMPERIODEND event See EVENTS_PWMPERIODEND H Disabled 0 Disable Enabled 1 Enable RW LOOPSDONE Enable or disab
47 PWM — Pulse width modulation Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id H G F E D C B Reset 0x00000000 Id RW Field 0 Value Id 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Description See EVENTS_LOOPSDONE Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled 47.5.
47 PWM — Pulse width modulation PWM module enable register Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id A Reset 0x00000000 Id RW Field A RW ENABLE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Description Disabled 0 Disabled Enabled 1 Enable Enable or disable PWM module 47.5.
47 PWM — Pulse width modulation Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id B Reset 0x00000000 Id RW Field A RW LOAD 0 Value Id A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Description How a sequence is read from RAM and spread to the compare register Common 0 1st half word (16-bit) used in all PWM channels 0..3 Grouped 1 1st half word (16-bit) used in channel 0..
47 PWM — Pulse width modulation Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000001 Id RW Field A RW CNT 0 Value Id 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Value Description Amount of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods) Continuous 0 Update every PWM period 47.5.14 SEQ[0].
47 PWM — Pulse width modulation Time added after the sequence Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 Id RW Field A RW CNT 0 Value Id 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Description Time added after the sequence in PWM periods 47.5.19 PSEL.
47 PWM — Pulse width modulation Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id B A A A A A Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Id RW Field B RW CONNECT Value Id Value Description Disconnected 1 Disconnect Connected 0 Connect Connection 47.6 Electrical specification 47.6.
48 SPI — Serial peripheral interface master 48 SPI — Serial peripheral interface master The SPI master provides a simple CPU interface which includes a TXD register for sending data and an RXD register for receiving data. This section is added for legacy support for now. PSEL.MISO MISO PSEL.SCK PSEL.MOSI RXD-1 TXD+1 RXD TXD MOSI READY Figure 150: SPI master RXD-1 and TXD+1 illustrate the double buffered version of RXD and TXD respectively. 48.
48 SPI — Serial peripheral interface master always be connected to a pin, and that pin's input buffer must always be connected for the SPI to work. This configuration must be retained in the GPIO for the selected IOs as long as the SPI is enabled. Only one peripheral can be assigned to drive a particular GPIO pin at a time, failing to do so may result in unpredictable behavior.
48 SPI — Serial peripheral interface master CSN n-1 n MISO A B C m-2 m-1 m 6 7 m-1 = RXD m = RXD TXD = n 5 m-2 = RXD TXD = n-1 C = RXD 4 B = RXD TXD = 2 TXD = 1 3 TXD = n-2 2 A = RXD 1 TXD = 0 CPU READY n-2 READY 2 READY 1 READY 0 READY MOSI READY SCK Figure 151: SPI master transaction The READY event of the third byte transaction is delayed until B is extracted from RXD in occurrence number 3 on the horizontal lifeline.
48 SPI — Serial peripheral interface master 48.
48 SPI — Serial peripheral interface master 48.2.3 ENABLE Address offset: 0x500 Enable SPI Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id A A A A Reset 0x00000000 Id RW Field A RW ENABLE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Description Disabled 0 Disable SPI Enabled 1 Enable SPI Enable or disable SPI 48.2.
48 SPI — Serial peripheral interface master 48.2.8 PSEL.MOSI Address offset: 0x50C Pin select for MOSI Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id Reset 0xFFFFFFFF Id RW Field A RW PSELMOSI 1 Value Id Disconnected AA A A A A A A AAAA A A A A A A A A A A A A A A A A A A A A 1 1 1 1 1 1 1 1111 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value Description [0..31] Pin number configuration for SPI MOSI signal 0xFFFFFFFF Disconnect 48.2.
48 SPI — Serial peripheral interface master Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id Reset 0x04000000 Id AA A A A A A A AAAA A A A A A A A A A A A A A A A A A A A A 0 0 0 0 1 0 0 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW Field Value Id Value Description M2 0x20000000 2 Mbps M4 0x40000000 4 Mbps M8 0x80000000 8 Mbps 48.2.
48 SPI — Serial peripheral interface master Symbol Description Min. tSPI,WHSCK SCK high timea (0.5*tCSCK ) Typ. tSPI,WLSCK SCK low timea tSPI,SUMI MISO to CLK edge setup time tSPI,HMI CLK edge to MISO hold time tSPI,VMO CLK edge to MOSI valid tSPI,HMO MOSI hold time after CLK edge Max. Units – tRSCK (0.
49 TWI — I2C compatible two-wire interface 49 TWI — I2C compatible two-wire interface The TWI master is compatible with I2C operating at 100 kHz and 400 kHz. PSELSDA PSELSCL PSELSDA STARTRX RXDRDY STARTTX TXDSENT SUSPEND RXD (signal) RESUME RXD TXD BB TXD (signal) SUSPENDED ERROR STOP STOPPED Figure 154: TWI master's main features 49.1 Functional description This TWI master is not compatible with CBUS. The TWI transmitter and receiver are single buffered.
49 TWI — I2C compatible two-wire interface as long as the TWI master is enabled, and retained only as long as the device is in ON mode. PSELSCL and PSELSDA must only be configured when the TWI is disabled. To secure correct signal levels on the pins used by the TWI master when the system is in OFF mode, and when the TWI master is disabled, these pins must be configured in the GPIO peripheral as described in Table 124: GPIO configuration on page 523.
7 TXDSENT STOP TXD = N TXD = 2 6 4 STOPPED TXDSENT TXDSENT TXD = 1 TXD = 0 STARTTX TXDSENT TWI 3 STOP N ACK 2 N-1 ACK 2 ACK 1 ACK 0 ACK 1 ADDR ACK WRITE START CPU Lifeline 49 TWI — I2C compatible two-wire interface Figure 156: The TWI master writing data to a slave The TWI master write sequence is stopped when the STOP task is triggered whereupon the TWI master will generate a stop condition on the TWI bus. 49.
BB SHORT BB RXDRDY 4 5 M = RXD M-1 = RXD RESUME A = RXD 3 RESUME STARTRX 2 STOPPED STOP RXDRDY SUSPENDED SUSPENDED RXDRDY SUSPEND SHORT BB SHORT RXDRDY SUSPENDED SUSPEND BB SUSPEND SHORT TWI Lifeline CPU Lifeline STOP 1 M NACK M-1 ACK B ACK A ACK ACK ADDR READ START TWI 49 TWI — I2C compatible two-wire interface Figure 157: The TWI master reading data from a slave 49.
49 TWI — I2C compatible two-wire interface To generate a repeated start after a read sequence, a second start task must be triggered instead of the STOP task, that is, STARTRX or STARTTX. This start task must be triggered before the last byte is extracted from RXD to ensure that the TWI master sends a NACK back to the slave before generating the repeated start condition. 49.
49 TWI — I2C compatible two-wire interface Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id B A Reset 0x00000000 Id RW Field 0 Value Id 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Description See EVENTS_BB and TASKS_SUSPEND B Disabled 0 Disable shortcut Enabled 1 Enable shortcut RW BB_STOP Shortcut between BB event and STOP task See EVENTS_BB and TASKS_STOP Disabled 0 Disable shortcut Enabled 1 Enable shortcut
49 TWI — I2C compatible two-wire interface Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id F Reset 0x00000000 Id RW Field A RW STOPPED 0 Value Id E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Description Write '1' to Disable interrupt for STOPPED event See EVENTS_STOPPED B Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW RXDREADY Write '1' to Disable interrupt for RXDREADY even
49 TWI — I2C compatible two-wire interface Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id C B A Reset 0x00000000 Id RW Field 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Id Value Present 1 Read: error present Description Clear 1 Write: clear error on writing '1' 49.8.
49 TWI — I2C compatible two-wire interface Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id A A A A A A A A Reset 0x00000000 Id RW Field A RW TXD 0 Value Id 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Description TXD register 49.8.
49 TWI — I2C compatible two-wire interface Symbol Description Min. tTWI,HD_STA,250kbps TWI master hold time for START and repeated START condition, 4000 Typ. Max.
50 UART — Universal asynchronous receiver/ transmitter 50 UART — Universal asynchronous receiver/ transmitter PSELRXD PSELCTS PSELRTS PSELTXD STARTTX STARTRX STOPRX RXD (signal) RXD-5 TXD RXD-4 RXD-3 TXD (signal) STOPTX RXD-2 RXD-1 RXTO RXD RXDRDY TXDRDY Figure 160: UART configuration 50.1 Functional description Listed here are the main features of UART.
50 UART — Universal asynchronous receiver/ transmitter 50.3 Shared resources The UART shares registers and other resources with other peripherals that have the same ID as the UART. Therefore, you must disable all peripherals that have the same ID as the UART before the UART can be configured and used. Disabling a peripheral that has the same ID as the UART will not reset any of the registers that are shared with the UART.
50 UART — Universal asynchronous receiver/ transmitter The RTS signal will first be activated again when the FIFO has been emptied, that is, when all bytes in the FIFO have been read by the CPU, see Figure 162: UART reception on page 534. The RTS signal will also be deactivated when the receiver is stopped through the STOPRX task as illustrated in Figure 162: UART reception on page 534.
50 UART — Universal asynchronous receiver/ transmitter 50.8 Using the UART without flow control If flow control is not enabled, the interface will behave as if the CTS and RTS lines are kept active all the time. 50.9 Parity configuration When parity is enabled, the parity will be generated automatically from the even parity of TXD and RXD for transmission and reception respectively. 50.
50 UART — Universal asynchronous receiver/ transmitter Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id B A Reset 0x00000000 Id RW Field 0 Value Id 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Description See EVENTS_CTS and TASKS_STARTRX B Disabled 0 Disable shortcut Enabled 1 Enable shortcut RW NCTS_STOPRX Shortcut between NCTS event and STOPRX task See EVENTS_NCTS and TASKS_STOPRX Disabled 0 Disable shortcut En
50 UART — Universal asynchronous receiver/ transmitter Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id F Reset 0x00000000 Id RW Field A RW CTS 0 Value Id E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Description Write '1' to Disable interrupt for CTS event See EVENTS_CTS B Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled RW NCTS Write '1' to Disable interrupt for NCTS event See EVE
50 UART — Universal asynchronous receiver/ transmitter Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id D C B A Reset 0x00000000 Id RW Field 0 Value Id 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value Description A valid stop bit is not detected on the serial data input after all bits in a character have been received.
50 UART — Universal asynchronous receiver/ transmitter Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id Reset 0xFFFFFFFF Id RW Field A RW PSELCTS 1 Value Id Disconnected AA A A A A A A AAAA A A A A A A A A A A A A A A A A A A A A 1 1 1 1 1 1 1 1111 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value Description [0..31] Pin number configuration for UART CTS signal 0xFFFFFFFF Disconnect 50.10.
50 UART — Universal asynchronous receiver/ transmitter Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id Reset 0x04000000 Id AA A A A A A A AAAA A A A A A A A A A A A A A A A A A A A A 0 0 0 0 1 0 0 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW Field Value Id Value Description Baud76800 0x013A9000 76800 baud (actual rate: 76923) Baud115200 0x01D7E000 115200 baud (actual rate: 115942) Baud230400 0x03AFB000 230400 baud (actual rate:
51 Mechanical specifications 51 Mechanical specifications The mechanical specifications for the packages show the dimensions in millimeters. 51.1 QFN48 6 x 6 mm package Figure 163: QFN48 6 x 6 mm package Table 130: QFN48 dimensions in millimeters Package QFN48 (6x6) A A1 0.80 0.00 0.85 0.02 0.90 0.05 A3 b D, E 0.15 0.2 0.20 D2, E2 e 4.50 6.0 0.25 Page 541 4.60 4.70 0.4 K L 0.20 0.35 Min. 0.40 Nom. 0.45 Max.
51 Mechanical specifications 51.2 WLCSP package Figure 164: WLCSP package Table 131: WLCSP packet dimensions in millimeters Package WLCSP (3.0 × 3.2) A A1 0.351 0.13 0.375 0.15 0.399 0.17 A3 b D E D2 E2 e K L 2.956 3.226 2.4 2.8 0.4 1.4 1.2 Min. 0.19 0.225 0.20 Nom. Max. 0.
52 Ordering information 52 Ordering information This chapter contains information on IC marking, ordering codes, and container sizes. 52.1 IC marking The nRF52832 IC package is marked like described below. N 5 2 8
3 2
52 Ordering information Figure 167: Outer box label 52.3 Order code Here are the nRF52832 order codes and definitions. n R F 5 2 8 3 2 -
Figure 168: Order code Table 132: Abbreviations Abbreviation N52/nRF52 832 Definition and implemented codes nRF52 Series product Part code Package variant code Function variant code Build code H - Hardware version code P - Production configuration code (production site, etc.
52 Ordering information Table 133: Package variant codes QF CI Package QFN WLCSP Size (mm) 6x6 3.0 x 3.2 Pin/Ball count 48 50 Pitch (mm) 0.4 0.4 Table 134: Function variant codes AA AB Flash (kB) 512 256 RAM (kB) 64 32 Table 135: Hardware version codes [A . . Z] Description Hardware version/revision identifier (incremental) Table 136: Production configuration codes [0 . . 9] [A . .
53 Reference circuitry 53 Reference circuitry To ensure good RF performance when designing PCBs, it is highly recommended to use the PCB layouts and component values provided by Nordic Semiconductor. Documentation for the different package reference circuits, including Altium Designer files, PCB layout files, and PCB production files can be downloaded from Reference layout nRF52 Series. 53.1 Schematic QFAA and QFAB QFN48 with internal LDO setup C9 4.7µF C2 VDD DCC DEC4 VSS N.C. P0.31/AIN7 P0.
53 Reference circuitry 53.2 Schematic QFAA and QFAB QFN48 with DC/DC regulator setup L3 15nH C10 1.0µF VDD_nRF 12pF C9 4.7µF VDD DCC DEC4 VSS N.C. P0.31/AIN7 P0.30/AIN6 P0.29/AIN5 P0.28/AIN4 P0.27 P0.26 P0.25 X2 32.768kHz C12 C2 12pF nRF52832 VDD XC2 XC1 DEC3 DEC2 VSS ANT P0.24 P0.23 P0.22 SWDIO SWDCLK VDD P0.11 P0.12 P0.13 P0.14 P0.15 P0.16 P0.17 P0.18 P0.19 P0.20 P0.21/RESET DEC1 P0.00/XL1 P0.01/XL2 P0.02/AIN0 P0.03/AIN1 P0.04/AIN2 P0.05/AIN3 P0.06 P0.07 P0.08 P0.09 P0.
53 Reference circuitry 53.3 Schematic QFAA and QFAB QFN48 with DC/DC regulator and NFC setup L3 15nH C10 1.0µF VDD_nRF 12pF C9 4.7µF VDD DCC DEC4 VSS N.C. P0.31/AIN7 P0.30/AIN6 P0.29/AIN5 P0.28/AIN4 P0.27 P0.26 P0.25 X2 32.768kHz C12 12pF C_tune1 TBD 1 P0.00/XL1 2 P0.01/XL2 3 P0.02/AIN0 4 P0.03/AIN1 5 P0.04/AIN2 6 P0.05/AIN3 7 P0.06 8 P0.07 9 P0.08 10 11 12 DEC1 P0.00/XL1 P0.01/XL2 P0.02/AIN0 P0.03/AIN1 P0.04/AIN2 P0.05/AIN3 P0.06 P0.07 P0.08 P0.09 P0.
53 Reference circuitry 53.4 Schematic CIAA WLCSP with internal LDO setup C8 4.7µF C2 12pF X1 32MHz C1 A7 B6 A6 C5 C4 B5 A5 A4 A3 B4 D3 B3 C4 100nF 12pF X2 32.768kHz VDD DCC DEC4 VSS VSS P0.31/AIN7 P0.30/AIN6 P0.29/AIN5 P0.28/AIN4 P0.27 P0.26 P0.25 C11 VDD_nRF DEC4 DEC1 C10 12pF nRF52832 XC2 XC1 DEC3 DEC2 VSS_PA ANT P0.24 P0.23 P0.22 SWDIO SWDCLK VDD P0.11 P0.12 P0.13 P0.14 P0.15 P0.16 P0.17 P0.18 P0.19 P0.20 P0.21/RESET DEC1 P0.00/XL1 P0.01/XL2 P0.02/AIN0 P0.03/AIN1 P0.04/AIN2 P0.05/AIN3 P0.
53 Reference circuitry 53.5 Schematic CIAA WLCSP with DC/DC regulator setup L3 15nH C9 1.0µF C11 C8 4.7µF C2 12pF X1 32MHz C1 A7 B6 A6 C5 C4 B5 A5 A4 A3 B4 D3 B3 C4 100nF X2 32.768kHz 12pF nRF52832 XC2 XC1 DEC3 DEC2 VSS_PA ANT P0.24 P0.23 P0.22 SWDIO SWDCLK VDD P0.11 P0.12 P0.13 P0.14 P0.15 P0.16 P0.17 P0.18 P0.19 P0.20 P0.21/RESET DEC1 P0.00/XL1 P0.01/XL2 P0.02/AIN0 P0.03/AIN1 P0.04/AIN2 P0.05/AIN3 P0.06 P0.07 P0.08 P0.09 P0.10 N.C. VSS VSS VDD_nRF H7 F4 H6 G4 H5 H4 H3 G3 H2 F3 G2 H1 B7 P0.
53 Reference circuitry 53.6 Schematic CIAA WLCSP with DC/DC regulator and NFC setup L3 15nH C9 1.0µF 12pF C8 4.7µF 12pF B7 P0.00/XL1 D7 P0.01/XL2 C7 P0.02/AIN0C6 P0.03/AIN1D6 P0.04/AIN2E6 Ctune2 TBD Note: The value of C_tune1 and C_tune2 must be tuned to match the selected NFC antenna. 12pF C7 nRF52832 XC2 XC1 DEC3 DEC2 VSS_PA ANT P0.24 P0.23 P0.22 SWDIO SWDCLK VDD P0.11 P0.12 P0.13 P0.14 P0.15 P0.16 P0.17 P0.18 P0.19 P0.20 P0.21/RESET Ctune1 TBD P0.06 P0.07 P0.08 DEC1 P0.00/XL1 P0.01/XL2 P0.
53 Reference circuitry matching circuitry (components between device pin ANT and the antenna) to reduce the stray capacitances that influence RF performance. A matching network is needed between the RF pin ANT and the antenna, to match the antenna impedance (normally 50 ohm) to the optimum RF load impedance for the chip. For optimum performance, the impedance for the matching network should be set as described in the recommended package reference circuitry in Reference circuitry on page 546 above.
53 Reference circuitry Figure 176: Top layer Figure 177: Bottom layer Important: No components in bottom layer.
54 Liability disclaimer 54 Liability disclaimer Nordic Semiconductor ASA reserves the right to make changes without further notice to the product to improve reliability, function or design. Nordic Semiconductor ASA does not assume any liability arising out of the application or use of any product or circuits described herein. 54.
Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: FCC Statement 2.2 List of applicable FCC rules：FCC Part15 Subpart C, Section 15.247 Information on test modes and additional testing requirements To investigate the maximum EMI emission characteristics generates from EUT, the test system was pre-scanning tested base on the consideration of following EUT operation mode or test configuration mode which possible have effect on EMI emission level.
FCC Radiation Exposure Statement: This equipment complies with FCC radiation exposure limits set forth for an uncontrolled environment. This equipment should be installed and operated with minimum distance 20cm between the radiator & your body.
Antennas Antenna Type: PCB Antenna Antenna Gain(Peak): 0 dBi RF exposure considerations This equipment complies with FCC radiation exposure limits set forth for an uncontrolled environment. This equipment should be installed and operated with a minimum distance of 20cm between the radiator & your body. This transmitter must not be co-located or operating in conjunction with any other antenna or transmitter.
installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation.
