Product Specs

19 CLOCK — Clock control
Page
108
19.3.8 LFCLKSRC
Address offset: 0x518
Clock source for the LFCLK
Bit number
Id
Reset 0x00000000
31 30
0 0
29
0
28
0
27
0
26
0
25
0
24
0
23 22 21 20
0 0 0 0
19
0
18
0
17
C
0
16
B
0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
A
0
0
A
0
Id RW Field
Value Id
Value
Description
A
RW
SRC
RC
0
Clock source
32.768 kHz RC oscillator
Xtal
1
32.768 kHz crystal oscillator
Synth
2
32.768 kHz synthesized from HFCLK
B
RW
BYPASS
Disabled
0
Enable or disable bypass of LFCLK crystal oscillator with external
clock source
Disable (use with Xtal or low-swing external source)
Enabled
1
Enable (use with rail-to-rail external source)
C
RW
EXTERNAL
Enable or disable external source for LFCLK
Disabled
0
Disable external source (use with Xtal)
Enabled
1
Enable use of external source instead of Xtal (SRC needs to be
set to Xtal)
19.3.9 CTIV ( Retained )
Address offset: 0x538
This register is a retained register
Calibration timer interval
Bit number
Id
Reset 0x00000000
31 30
0 0
29
0
28
0
27
0
26
0
25
0
24
0
23 22 21 20
0 0 0 0
19
0
18
0
17
0
16
0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
A
0
5
A
0
4
A
0
3
A
0
2
A
0
1
A
0
0
A
0
Id RW Field
Value Id
Value
Description
A RW CTIV Calibration timer interval in multiple of 0.25 seconds. Range:
0.25 seconds to 31.75 seconds.
19.3.10 TRACECONFIG
Address offset: 0x55C
Clocking options for the Trace Port debug interface
This register is a retained register. Reset behavior is the same as debug components.
Bit number
Id
Reset 0x00000000
31 30
0 0
29
0
28
0
27
0
26
0
25
0
24
0
23 22 21 20
0 0 0 0
19
0
18
0
17
B
0
16
B
0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
A
0
0
A
0
Id RW Field
Value Id
Value
Description
A RW TRACEPORTSPEED
Speed of Trace Port clock. Note that the TRACECLK pin will
output this clock divided by two.
32MHz
0
32 MHz Trace Port clock (TRACECLK = 16 MHz)
16MHz
1
16 MHz Trace Port clock (TRACECLK = 8 MHz)
8MHz
2
8 MHz Trace Port clock (TRACECLK = 4 MHz)
4MHz
3
4 MHz Trace Port clock (TRACECLK = 2 MHz)
B RW TRACEMUX
GPIO
0
Pin multiplexing of trace signals.
GPIOs multiplexed onto all trace-pins
Serial
Parallel
1
2
SWO multiplexed onto P0.18, GPIO multiplexed onto other
trace pins
TRACECLK and TRACEDATA multiplexed onto P0.20, P0.18,
P0.16, P0.15 and P0.14.