Product Specs

20 GPIO — General purpose input/output
Page
112
PIN[0].OUT
DETECT
DETECTMODE
LDETECT
LATCH
ANAEN
DIR_OVERRIDE
OUT_OVERRIDE
OUT
PIN0.DETECT
PIN1.DETECT
Sense
PIN[0].CNF.SENSE
PIN0
PIN[0].CNF.DRIVE
O
PIN[0].CNF.PULL
PIN[0].CNF.DIR
GPIO Port
PIN0
PIN[0].OUT
PIN[0].IN
PIN[0].CNF
..
PIN0
PIN31.DETECT
IN
PIN[0].IN
PIN[0].CNF.INPUT
I
PIN31
PIN[31].OUT
PIN[31].IN
PIN31
INPUT_OVERRIDE
PIN[31].CNF
ANAIN
O: output buffer I: input buffer
Figure 21: GPIO Port and the GPIO pin details
Figure 21: GPIO Port and the GPIO pin details on page 112 illustrates the GPIO port containing 32
individual pins, where PIN0 is illustrated in more detail as a reference. All the signals on the left side of the
illustration are used by other peripherals in the system, and therefore, are not directly available to the CPU.
Make sure that a pin is in a level that cannot trigger the sense mechanism before enabling it. Detect will
go high immediately if the sense condition configured in the PIN_CNF registers is met when the sense
mechanism is enabled. This will trigger a PORT event if the DETECT signal was low before enabling the
sense mechanism. See GPIOTE — GPIO tasks and events on page 157.
See the following peripherals for more information about how the DETECT signal is used:
• POWER: uses the DETECT signal to exit from System OFF.
• GPIOTE: uses the DETECT signal to generate the PORT event.
When a pin's PINx.DETECT signal goes high, a flag will be set in the LATCH register, e.g. when the
PIN0.DETECT signal goes high, bit 0 in the LATCH register will be set to '1'.
The LATCH register will only be cleared if the CPU explicitly clears it by writing a '1' to the bit that shall be
cleared, i.e. the LATCH register will not be affected by a PINx.DETECT signal being set low.
If the CPU performs a clear operation on a bit in the LATCH register when the associated PINx.DETECT
signal is high, the bit in the LATCH register will not be cleared.
The LDETECT signal will be set high when one or more bits in the LATCH register are '1'. The LDETECT
signal will be set low when all bits in the LATCH register are successfully cleared to '0'.
If one or more bits in the LATCH register are '1' after the CPU has performed a clear operation on the
LATCH registers, a rising edge will be generated on the LDETECT signal, this is illustrated in Figure 22:
DETECT signal behavior on page 113.
Important: The CPU can read the LATCH register at any time to check if a SENSE condition has
been met on one or more of the the GPIO pins even if that condition is no longer met at the time the
CPU queries the LATCH register. This mechanism will work even if the LDETECT signal is not used
as the DETECT signal.
The LDETECT signal is by default not connected to the GPIO port's DETECT signal, but via the
DETECTMODE register it is possible to change the behaviour of the GPIO port's DETECT signal from the
default behaviour described above to instead be derived directly from the LDETECT signal, see Figure 21:
GPIO Port and the GPIO pin details on page 112. Figure 22: DETECT signal behavior on page 113
illustrates the DETECT signals behaviour for these two alternatives.