Product Specs

20 GPIO — General purpose input/output
Page
113
1
2
3
4
PIN31.DETECT
PIN1.DETECT
PIN0.DETECT
DETECT
(Default mode)
LATCH.31
LATCH.1
LATCH.0
DETECT
(LDETECT mode)
Figure 22: DETECT signal behavior
The input buffer of a GPIO pin can be disconnected from the pin to enable power savings when the pin is
not used as an input, see Figure 21: GPIO Port and the GPIO pin details on page 112. Inputs must be
connected in order to get a valid input value in the IN register and for the sense mechanism to get access to
the pin.
Other peripherals in the system can attach themselves to GPIO pins and override their output value and
configuration, or read their analog or digital input value, see Figure 21: GPIO Port and the GPIO pin details
on page 112.
Selected pins also support analog input signals, see ANAIN in Figure 21: GPIO Port and the GPIO pin
details on page 112. The assignment of the analog pins can be found in Pin assignments on page 13.
Important: When a pin is configured as digital input, care has been taken in the nRF52832 design
to minimize increased current consumption when the input voltage is between V
IL
and V
IH
. However,
it is a good practice to ensure that the external circuitry does not drive that pin to levels between V
IL
and V
IH
for a long period of time.
20.2 GPIO located near the RADIO
Radio performance parameters, such as sensitivity, may be affected by high frequency digital I/O with large
sink/source current close to the radio power supply and antenna pins.
Refer to Pin assignments on page 13 for recommended usage guidelines to maximize radio performance in
an application.
20.3 Registers
Table 28: Instances
Base address
Peripheral
Instance
Description
Configuration
0x50000000
GPIO
GPIO
General purpose input and output
Deprecated
0x50000000
GPIO
P0
General purpose input and output
CPU
LATCH = (1<<0)
LATCH = (1<<1)
LATCH = (1<<1)
LATCH = (1 << 31)