Product Specs

21 GPIOTE — GPIO tasks and events
Page
158
When setting the CONFIG[n] registers, MODE=Disabled does not have the same effect as MODE=Task and
POLARITY=None. In the latter case, a CLR or SET task occurring at the exact same time as OUT will end
up with no change on the pin, according to the priorities described in the table above.
When a GPIOTE channel is configured to operate on a pin as a task, the initial value of that pin is configured
in the OUTINIT field of CONFIG[n].
21.2 Port event
PORT is an event that can be generated from multiple input pins using the GPIO DETECT signal.
The event will be generated on the rising edge of the DETECT signal. See GPIO — General purpose input/
output on page 111 for more information about the DETECT signal.
Putting the system into System ON IDLE while DETECT is high will not cause DETECT to wake the system
up again. Make sure to clear all DETECT sources before entering sleep. If the LATCH register is used as a
source, if any bit in LATCH is still high after clearing all or part of the register (for instance due to one of the
PINx.DETECT signal still high), a new rising edge will be generated on DETECT, see Pin configuration on
page 111.
Trying to put the system to System OFF while DETECT is high will cause a wakeup from System OFF reset.
This feature is always enabled although the peripheral itself appears to be IDLE, that is, no clocks or other
power intensive infrastructure have to be requested to keep this feature enabled. This feature can therefore
be used to wake up the CPU from a WFI or WFE type sleep in System ON with all peripherals and the CPU
idle, that is, lowest power consumption in System ON mode.
In order to prevent spurious interrupts from the PORT event while configuring the sources, the user
shall first disable interrupts on the PORT event (through INTENCLR.PORT), then configure the sources
(PIN_CNF[n].SENSE), clear any potential event that could have occurred during configuration (write '1' to
EVENTS_PORT), and finally enable interrupts (through INTENSET.PORT).
21.3 Tasks and events pin configuration
Each GPIOTE channel is associated with one physical GPIO pin through the CONFIG.PSEL field.
When Event mode is selected in CONFIG.MODE, the pin specified by CONFIG.PSEL will be configured as
an input, overriding the DIR setting in GPIO. Similarly, when Task mode is selected in CONFIG.MODE, the
pin specified by CONFIG.PSEL will be configured as an output overriding the DIR setting and OUT value
in GPIO. When Disabled is selected in CONFIG.MODE, the pin specified by CONFIG.PSEL will use its
configuration from the PIN[n].CNF registers in GPIO.
Only one GPIOTE channel can be assigned to one physical pin. Failing to do so may result in unpredictable
behavior.
21.4 Registers
Table 32: Instances
Base address
Peripheral
Instance
Description
Configuration
0x40006000
GPIOTE
GPIOTE
GPIO Tasks and Events
Table 33: Register Overview
Register
Offset
Description
TASKS_OUT[0]
0x000
Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is configured in
CONFIG[0].POLARITY.
TASKS_OUT[1]
0x004
Task for writing to pin specified in CONFIG[1].PSEL. Action on pin is configured in
CONFIG[1].POLARITY.