Product Specs

22 PPI — Programmable peripheral interconnect
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CH[1].EEP
CH[0].EEP
Event 1
Event 2
CH[n].EEP
Event 1
Event 2
Event 3
CHEN
CHG[0] ... CHG[m]
16MHz
Task 1
Task 1
Task 2
Task 3
n
n
n
1
1
1
0
0
0
Peripheral 2
Peripheral 1
Peripheral 2
Peripheral 1
Instance Channel Number of channels Number of groups
22 PPI — Programmable peripheral interconnect
The Programmable peripheral interconnect (PPI) enables peripherals to interact autonomously with each
other using tasks and events independent of the CPU. The PPI allows precise synchronization between
peripherals when real-time application constraints exist and eliminates the need for CPU activity to
implement behavior which can be predefined using PPI.
CH[0].TEP
Figure 28: PPI block diagram
FORK[0].TEP
The PPI system has, in addition to the fully programmable peripheral interconnections, a set of channels
where the event end point (EEP) and task end points (TEP) are fixed in hardware. These fixed channels
can be individually enabled, disabled, or added to PPI channel groups in the same way as ordinary PPI
channels.
Table 34: Configurable and fixed PPI channels
PPI 0-19 20 6
PPI (fixed) 20-31 12
The PPI provides a mechanism to automatically trigger a task in one peripheral as a result of an event
occurring in another peripheral. A task is connected to an event through a PPI channel. The PPI channel
is composed of three end point registers, one EEP and two TEPs. A peripheral task is connected to a TEP
using the address of the task register associated with the task. Similarly, a peripheral event is connected to
an EEP using the address of the event register associated with the event.
On each PPI channel, the signals are synchronized to the 16 MHz clock, to avoid any internal violation of
setup and hold timings. As a consequence, events that are synchronous to the 16 MHz clock will be delayed
by one clock period, while other asynchronous events will be delayed by up to one 16 MHz clock period.