Product Specs

Contents
Page
2
Contents
1 Revision history 9
2 About this document 10
2.1 Peripheral naming and abbreviations.............................................................................................10
2.2 Register tables 10
2.3 Registers 11
3 Block diagram 12
4 Pin assignments 13
4.1 QFN48 pin assignments 13
4.2 WLCSP ball assignments 15
4.3 GPIO usage restrictions 17
5 Absolute maximum ratings 19
6 Recommended operating conditions.......................................................................... 20
7 CPU 21
7.1 Floating point interrupt 21
7.2 Electrical specification 21
7.3 CPU and support module configuration.........................................................................................22
8 Memory 23
8.1 RAM - Random access memory 23
8.2 Flash - Non-volatile memory 24
8.3 Memory map 24
8.4 Instantiation 24
9 AHB multilayer 26
9.1 AHB multilayer priorities 26
10 EasyDMA 27
10.1 EasyDMA array list 28
11 NVMC — Non-volatile memory controller
...............................................................
29
11.1 Writing to Flash 29
11.2 Erasing a page in Flash 29
11.3 Writing to user information configuration registers (UICR).......................................................29
11.4 Erasing user information configuration registers (UICR).......................................................... 29
11.5 Erase all 30
11.6 Cache 30
11.7 Registers 30
11.8 Electrical specification 33
12 BPROT — Block protection 34
12.1 Registers 34
13 FICR — Factory information configuration registers
...........................................
43
13.1 Registers 43
14 UICR — User information configuration registers
................................................
54
14.1 Registers 54
15 Peripheral interface 68
15.1 Peripheral ID 68
15.2 Peripherals with shared ID 68
15.3 Peripheral registers 69
15.4 Bit set and clear 69
15.5 Tasks 69
15.6 Events 70
15.7 Shortcuts 70
15.8 Interrupts 70