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Table Of Contents

1Revision history
2About this document
- 2.1Peripheral naming and abbreviations
- 2.2Register tables
  - 2.2.1Fields and values
- 2.3Registers
3Block diagram
4Pin assignments
- 4.1QFN48 pin assignments
- 4.2WLCSP ball assignments
  - Figure 3: WLCSP ball assignments, top view Table 3
- 4.3GPIO usage restrictions
  - 4.3.1GPIO located near the radio
    - Table 4: GPIO recommended usage for QFN48 package
  - 4.3.2NFC antenna pins
    - Table 6: GPIO pins used by NFC
5Absolute maximum ratings
6Recommended operating conditions
- Table 8: Recommended operating conditions
7CPU
- 7.1Floating point interrupt
- 7.2Electrical specification
  - 7.2.1CPU performance
- 7.3CPU and support module configuration
8Memory
- Figure 4: Memory layout
- 8.1RAM - Random access memory
- 8.2Flash - Non-volatile memory
- 8.3Memory map
- 8.4Instantiation
  - Table 10: Instantiation table
9AHB multilayer
- 9.1AHB multilayer priorities
10EasyDMA
- Figure 6: EasyDMA example
- Figure 7: EasyDMA memory layout
- 10.1EasyDMA array list
11NVMC — Non-volatile memory controller
- 11.1Writing to Flash
- 11.2Erasing a page in Flash
- 11.3Writing to user information configuration register
- 11.4Erasing user information configuration registers (
- 11.5Erase all
- 11.6Cache
- 11.7Registers
12BPROT — Block protection
- 12.1Registers
13FICR — Factory information configuration registers
- 13.1Registers
14UICR — User information configuration registers
- 14.1Registers
15Peripheral interface
- 15.1Peripheral ID
- 15.2Peripherals with shared ID
- 15.3Peripheral registers
- 15.4Bit set and clear
- 15.5Tasks
- 15.6Events
- 15.7Shortcuts
- 15.8Interrupts
  - 15.8.1Interrupt clearing
16Debug and trace
- Figure 11: Debug and trace overview
- 16.1DAP - Debug Access Port
  - Important:
- 16.2CTRL-AP - Control Access Port
  - 16.2.1Registers
- 16.3Debug interface mode
- 16.4Real-time debug
- 16.5Trace
  - 16.5.1Electrical specification
17Power and clock management
- Figure 12: Power Management Unit
- 17.1Current consumption scenarios
  - Table 22: Current consumption scenarios, common co
  - Current consumption: Radio
18POWER — Power supply
- 18.1Regulators
  - Figure 13: LDO regulator setup
- 18.2System OFF mode
  - 18.2.1Emulated System OFF mode
- 18.3System ON mode
  - 18.3.1Sub power modes
- 18.4Power supply supervisor
  - Figure 16: Power-fail comparator (BOR = Brownout r
- 18.5RAM sections
- 18.6Reset
- 18.7Retained registers
- 18.8Reset behavior
- 18.9Registers
- 18.10Electrical specification
  - 18.10.1Current consumption, sleep
  - 18.10.3Power fail comparator
19CLOCK — Clock control
- 19.1HFCLK clock controller
  - 19.1.164 MHz crystal oscillator (HFXO)
    - Figure 18: Circuit diagram of the 64 MHz crystal o
- 19.2LFCLK clock controller
- 19.3Registers
- 19.4Electrical specification
20GPIO — General purpose input/output
- 20.1Pin configuration
  - Figure 21: GPIO Port and the GPIO pin details
  - Figure 22: DETECT signal behavior
- 20.2GPIO located near the RADIO
- 20.3Registers
- 20.4Electrical specification
  - 20.4.1GPIO Electrical Specification
21GPIOTE — GPIO tasks and events
- Table 30: GPIOTE properties
- 21.1Pin events and tasks
  - Table 31: Task priorities
- 21.2Port event
- 21.3Tasks and events pin configuration
- 21.4Registers
- 21.5Electrical specification
22PPI — Programmable peripheral interconnect
- CH[0].TEP
- FORK[0].TEP
  - Table 34: Configurable and fixed PPI channels
- 22.1Pre-programmed channels
23RADIO — 2.4 GHz Radio
- Figure 29: RADIO block diagram
- 23.1EasyDMA
- 23.2Packet configuration
  - Figure 30: On-air packet layout
  - Figure 31: In-RAM representation of radio packet,
- 23.3Maximum packet length
- 23.4Address configuration
- 23.5Data whitening
  - Figure 32: Data whitening and de-whitening
- 23.6CRC
  - Figure 33: CRC generation of an n bit CRC
- 23.7Radio states
  - Table 39: RADIO state diagram
- 23.8Transmit sequence
  - Figure 35: Transmit sequence
  - Figure 36: Transmit sequence using sho
- 23.9Receive sequence
  - Figure 38: Receive sequence
  - Figure 39: Receive sequence using shortc
- 23.10Received Signal Strength Indicator (RSSI)
- 23.11Interframe spacing
- 23.12Device address match
- 23.13Bit counter
- 23.14Registers
- 23.15Electrical specification
24TIMER — Timer/counter
- Figure 42: Block schematic for timer/counter
- 24.1Capture
- 24.2Compare
- 24.3Task delays
- 24.4Task priority
- 24.5Registers
- 24.6Electrical specification
25RTC — Real-time counter
- Figure 43: RTC block schematic
- 25.2Resolution versus overflow and the PRESCALER
- 25.3COUNTER register
  - Figure 44: Timing diagram - COUNTER_PRESCALER
- 25.4Overflow features
- 25.5TICK event
- 25.6Event control feature
- 25.7Compare feature
- 25.8TASK and EVENT jitter/delay
- 25.9Reading the COUNTER register
- 25.10Registers
  - Table 47: Instances
  - 25.10.7PRESCALER
26RNG — Random number generator
- Figure 58: Random number generator
- 26.1Bias correction
- 26.2Speed
- 26.3Registers
  - Table 49: Instances
- 26.4Electrical specification
27TEMP — Temperature sensor
- 27.1Registers
- 27.2Electrical specification
28ECB — AES electronic codebook mode encryption
- 28.1Shared resources
- 28.2EasyDMA
- 28.3ECB data structure
- 28.4Registers
  - Table 54: Instances
29CCM — AES CCM mode encryption
- Figure 59: Key-stream generation followed by encry
- 29.1Shared resources
- 29.2Encryption
- 29.3Decryption
- 29.4AES CCM and RADIO concurrent operation
- 29.5Encrypting packets on-the-fly in radio transmit mo
  - Figure 62: Configuration of on-the-fly encryption
- 29.6Decrypting packets on-the-fly in radio receive mod
  - Figure 64: Configuration of on-the-fly decryption
- 29.7CCM data structure
  - Table 57: CCM data structure overview
  - Table 58: Data structure for unencrypted packet
- 29.8EasyDMA and ERROR event
- 29.9Registers
  - Table 60: Instances
  - 29.9.10SCRATCHPTR
30AAR — Accelerated address resolver
- 30.1Shared resources
- 30.2EasyDMA
- 30.3Resolving a resolvable address
  - Figure 66: Resolvable address
- 30.4Use case example for chaining RADIO packet recepti
- 30.5IRK data structure
- 30.6Registers
- 30.7Electrical specification
  - 30.7.1AAR Electrical Specification
31SPIM — Serial peripheral interface master with Eas
- Figure 69: SPIM — SPI master with EasyDMA
- 31.1Shared resources
- 31.2EasyDMA
  - 31.2.1EasyDMA list
    - EasyDMA array list
- 31.3SPI master transaction sequence
- 31.4Low power
- 31.5Master mode pin configuration
- 31.6Registers
- 31.7Electrical specification
  - 31.7.1SPIM master interface
  - 31.7.2Serial Peripheral Interface Master (SPIM) electr
    - Figure 72: SPIM timing diagram
32SPIS — Serial peripheral interface slave with Easy
- Figure 73: SPI slave
- 32.1Shared resources
- 32.2EasyDMA
- 32.3SPI slave operation
- 32.4Pin configuration
- 32.5Registers
- 32.6Electrical specification
  - 32.6.1SPIS slave interface electrical specifications
    - Figure 75: SPIS timing diagram
33TWIM — I2C compatible two-wire interface master wi
- Figure 77: TWI master with EasyDMA
- Figure 78: A typical TWI setup comprising one mast
- 33.1Shared resources
- 33.2EasyDMA
  - 33.2.1EasyDMA list
    - EasyDMA array list
- 33.3Master write sequence
  - Figure 80: TWI master writing dat
- 33.4Master read sequence
- 33.5Master repeated start sequence
  - Figure 82: A repeated start sequenc
- 33.6Low power
- 33.7Master mode pin configuration
34TWIS — I2C compatible two-wire interface slave wit
- Figure 86: TWI slave with EasyDMA
- Figure 87: A typical TWI setup comprising one mast
- Figure 88: TWI slave state machine
- 34.1Shared resources
- 34.2EasyDMA
- 34.3TWI slave responding to a read command
- 34.4TWI slave responding to a write command
- 34.5Master repeated start sequence
- 34.6Terminating an ongoing TWI transaction
- 34.7Low power
- 34.8Slave mode pin configuration
- 34.9Registers
- 34.10Electrical specification
  - 34.10.1TWIS slave interface electrical specifications
35UARTE — Universal asynchronous receiver/ transmitt
- Figure 93: UARTE configuration
- 35.2EasyDMA
- 35.3Transmission
  - Figure 94: UARTE transmission
- 35.4Reception
  - Figure 95: UARTE reception
  - Figure 96: UARTE reception with forced stop
- 35.5Error conditions
- 35.6Using the UARTE without flow control
- 35.7Parity configuration
- 35.8Low power
- 35.9Pin configuration
- 35.10Registers
- 35.11Electrical specification
  - 35.11.1UARTE electrical specification
36QDEC — Quadrature decoder
- 36.1Sampling and decoding
- 36.2LED output
- 36.3Debounce filters
- 36.4Accumulators
- 36.5Output/input pins
- 36.6Pin configuration
- 36.8Electrical specification
37SAADC — Successive approximation analog-to- digita
- 37.1Shared resources
- 37.2Overview
  - Figure 98: Simplified ADC block diagram
- 37.3Digital output
  - V(P)
  - REFERENCE
- 37.4Analog inputs and channels
- 37.5Operation modes
- 37.6EasyDMA
  - Figure 101: ADC
- 37.7Resistor ladder
- 37.8Reference
- 37.9Acquisition time
- 37.10Limits event monitoring
  - Figure 104: Example of limits monitoring on ch
- 37.11Registers
- 37.12Electrical specification
  - 37.12.1SAADC Electrical Specification
- 37.13Performance factors
38COMP — Comparator
- Figure 109: Comparator overview
- 38.1Shared resources
- 38.2Differential mode
  - Figure 110: Comparator in differential mode
- 38.3Single-ended mode
  - Figure 112: Comparator in single-ended mode
  - Figure 113: Hysteresis example where VIN+ start
- 38.4Pin configuration
- 38.5Registers
- 38.6Electrical specification
  - 38.6.1COMP Electrical Specification
39LPCOMP — Low power comparator
- Figure 115: Low power comparator
- Figure 116: Effect of hysteresis on a noisy input
- 39.1Shared resources
- 39.2Pin configuration
- 39.3Registers
  - Table 93: Instances
- 39.4Electrical specification
40WDT — Watchdog timer
- 40.1Reload criteria
- 40.2Temporarily pausing the watchdog
- 40.3Watchdog reset
- 40.4Registers
  - Table 95: Instances
- 40.5Electrical specification
41SWI — Software interrupts
- 41.1Registers
42NFCT — Near field communication tag
- 42.1Overview
  - Figure 117: NFC block diagram
- 42.2Pin configuration
- 42.3EasyDMA
- 42.4Collision resolution
  - Table 98: NFCID1 byte allocation (top sent first o
- 42.5Frame timing controller
- 42.6Frame assembler
  - Figure 120: Frame assemble
- 42.7Frame disassembler
  - Figure 121: Frame disassemble illustration
- 42.8Antenna interface
- 42.9NFCT antenna recommendations
  - Figure 122: NFCT antenna recommendations
- 42.10Battery protection
- 42.11References
- 42.12Registers
- 42.13Electrical specification
  - 42.13.1NFCT Electrical Specification
    - Figure 123: NFCT timing parameters (Shortc
43PDM — Pulse density modulation interface
- 43.1Master clock generator
- 43.2Module operation
- 43.3Decimation filter
- 43.4EasyDMA
  - Table 101: DMA sample storage
- 43.5Hardware example
  - Figure 125: Example of a single PDM microphone, wi
  - Figure 126: Example of a single PDM microphone, wi
- 43.6Pin configuration
- 43.8Electrical specification
  - 43.8.1PDM Electrical Specification
44I2S — Inter-IC sound interface
- 44.1Mode
- 44.2Transmitting and receiving
- 44.3Left right clock (LRCK)
- 44.4Serial clock (SCK)
- 44.5Master clock (MCK)
- 44.6Width, alignment and format
  - Figure 132: I2S format. CONFIG.SWIDTH equalling ha
- 44.7EasyDMA
- 44.8Module operation
- 44.9Pin configuration
  - Table 106: GPIO configuration before enabling peri
- 44.10Registers
- 44.11Electrical specification
  - 44.11.1I2S timing specification
45MWU — Memory watch unit
- Table 110: Memory regions
- 45.1Registers
46EGU — Event generator unit
- Table 113: EGU configuration
- Table 114: Instances
- 46.2Electrical specification
47PWM — Pulse width modulation
- Figure 142: PWM up counter example - FallingEdge p
- Figure 143: PWM up-and-down counter example
- 47.2Decoder with EasyDMA
- 47.3Limitations
- 47.4Pin configuration
- 47.5Registers
- 47.6Electrical specification
48SPI — Serial peripheral interface master
- Figure 150: SPI master
- 48.1.2Shared resources
- 48.1.3SPI master transaction sequence
  - Figure 151: SPI master transaction
- 48.2Registers
- 48.3Electrical specification
  - 48.3.1SPI master interface
  - 48.3.2Serial Peripheral Interface (SPI) Master timing
49TWI — I2C compatible two-wire interface
- Figure 154: TWI master's main features
- 49.1Functional description
  - Figure 155: A typical TWI setup comprising one mas
- 49.2Master mode pin configuration
- 49.3Shared resources
- 49.4Master write sequence
  - Figure 156: The TWI master writing d
- 49.5Master read sequence
- 49.6Master repeated start sequence
  - Figure 158: A repeated
- 49.7Low power
- 49.8Registers
  - Table 125: Instances
  - 49.8.11ADDRESS
50UART — Universal asynchronous receiver/ transmitte
- 50.2Pin configuration
- 50.3Shared resources
- 50.4Transmission
- 50.5Reception
  - Figure 162: UART reception
- 50.6Suspending the UART
- 50.7Error conditions
- 50.8Using the UART without flow control
- 50.9Parity configuration
- 50.10Registers
  - Table 128: Instances
- 50.11Electrical specification
  - 50.11.1UART electrical specification
51Mechanical specifications
- 51.1QFN48 6 x 6 mm package
  - Figure 163: QFN48 6 x 6 mm package
- 51.2WLCSP package
  - Figure 164: WLCSP package
52Ordering information
- 52.1IC marking
- 52.2Box labels
  - Figure 166: Inner box label
- 52.3Order code
  - Figure 168: Order code Table 132: Abbreviations
- 52.4Code ranges and values
- 52.5Product options
  - Table 143: Development tools order code
53Reference circuitry
- 53.1Schematic QFAA and QFAB QFN48 with internal LDO se
  - Figure 169: QFAA and QFAB QFN48 with internal LDO
- 53.2Schematic QFAA and QFAB QFN48 with DC/DC regulato
  - Figure 170: QFAA and QFAB QFN48 with DC/DC regul
- 53.3Schematic QFAA and QFAB QFN48 with DC/DC regulato
  - Figure 171: QFAA and QFAB QFN48 with DC/DC regul
- 53.4Schematic CIAA WLCSP with internal LDO setup
  - Figure 172: CIAA WLCSP with internal LDO setup
- 53.5Schematic CIAA WLCSP with DC/DC regulator setup
  - Figure 173: CIAA WLCSP with DC/DC regulator setu
- 53.6Schematic CIAA WLCSP with DC/DC regulator and
  - Figure 174: CIAA WLCSP with DC/DC regulator
- 53.7PCB guidelines
- 53.8PCB layout example
  - Figure 175: Top silk layer
  - Figure 177: Bottom layer
54Liability disclaimer
- 54.1RoHS and REACH statement
- 54.2Life support applications
Mouser Electronics

22 PPI — Programmable peripheral interconnect

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