Product Specs

25 RTC — Real-time counter
Page
246
SysClk
LFClk
PRESC
0x000
COUNTER
N-1
N
N+1
N+2
> 62.5
ns
CC[0]
X
N+2
COMPARE[0]
0
1
Figure 50: Timing diagram - COMPARE_N+2
• If the COUNTER is N, writing N or N+1 to a CC register may not trigger a COMPARE event.
SysClk
LFClk
PRESC
0x000
COUNTER
N-2
N-1
N
N+1
>= 0
CC[0]
X
N+1
COMPARE[0]
0
Figure 51: Timing diagram - COMPARE_N+1
• If the COUNTER is N and the current CC register value is N+1 or N+2 when a new CC value is written,
a match may trigger on the previous CC value before the new value takes effect. If the current CC value
greater than N+2 when the new value is written, there will be no event due to the old value.
SysClk
LFClk
PRESC
0x000
COUNTER
N-2
N-1
N
N+1
>= 0
CC[0]
N
X
COMPARE[0]
0
1
Figure 52: Timing diagram - COMPARE_N-1
25.8 TASK and EVENT jitter/delay
Jitter or delay in the RTC is due to the peripheral clock being a low frequency clock (LFCLK) which is not
synchronous to the faster PCLK16M.
Registers in the peripheral interface, part of the PCLK16M domain, have a set of mirrored registers in the
LFCLK domain. For example, the COUNTER value accessible from the CPU is in the PCLK16M domain
and is latched on read from an internal register called COUNTER in the LFCLK domain. COUNTER is the
register which is actually modified each time the RTC ticks. These registers must be synchronised between
clock domains (PCLK16M and LFCLK).
The following is a summary of the jitter introduced on tasks and events. Figures illustrating jitter follow.