Product Specs

10 EasyDMA
Page
27
AHB Multilayer
Peripheral
AHB
AHB
EasyDMA
WRITER
Peripheral
Core
EasyDMA
READER
RAM
RAM
RAM
READERBUFFER_SIZE 5
WRITERBUFFER_SIZE 6
uint8_t readerBuffer[READERBUFFER_SIZE] at 0x20000000;
uint8_t writerBuffer[WRITERBUFFER_SIZE] at 0x20000005;
// Configuring the READER channel
MYPERIPHERAL->READER.MAXCNT = READERBUFFER_SIZE;
MYPERIPHERAL->READER.PTR = &readerBuffer;
// Configure the WRITER channel
MYPERIPHERAL->WRITER.MAXCNT = WRITEERBUFFER_SIZE;
MYPERIPHERAL->WRITER.PTR = &writerBuffer;
10 EasyDMA
EasyDMA is an easy-to-use direct memory access module that some peripherals implement to gain direct
access to Data RAM.
The EasyDMA is an AHB bus master similar to the CPU and it is connected to the AHB multilayer
interconnect for direct access to the Data RAM. The EasyDMA is not able to access the Flash.
A peripheral can implement multiple EasyDMA instances, for example to provide a dedicated channel for
reading data from RAM into the peripheral at the same time as a second channel is dedicated for writing data
to the RAM from the peripheral. This concept is illustrated in Figure 6: EasyDMA example on page 27
Figure 6: EasyDMA example
An EasyDMA channel is usually exposed to the user in the form illustrated below, but some variations may
occur:
This example shows a peripheral called MYPERIPHERAL that implements two EasyDMA channels, one
for reading, called READER, and one for writing, called WRITER. When the peripheral is started, it is here
assumed that the peripheral will read 5 bytes from the readerBuffer located in RAM at address 0x20000000,
process the data and then write no more than 6 bytes back to the writerBuffer located in RAM at address
0x20000005. The memory layout of these buffers is illustrated in Figure 7: EasyDMA memory layout on page
28.