Product Specs

11 NVMC — Non-volatile memory controller
Page
30
11.5 Erase all
When erase is enabled, the whole Flash and UICR can be erased in one operation by using the ERASEALL
register. ERASEALL will not erase the factory information configuration registers (FICR).
The time it takes to perform an ERASEALL command is specified by t
ERASEALL
The CPU is halted while the
NVMC performs the erase operation.
11.6 Cache
An instruction cache (I-Cache) can be enabled for the ICODE bus in the NVMC.
See the Memory map in Memory map on page 24 for the location of Flash.
A cache hit is an instruction fetch from the cache, and it has a 0 wait-state delay. The number of wait-states
for a cache miss, where the instruction is not available in the cache and needs to be fetched from Flash,
depends on the processor frequency and is shown in CPU on page 21
Enabling the cache can increase CPU performance and reduce power consumption by reducing the number
of wait cycles and the number of flash accesses. This will depend on the cache hit rate. Cache will use some
current when enabled. If the reduction in average current due to reduced flash accesses is larger than the
cache power requirement, the average current to execute the program code will reduce.
When disabled, the cache does not use current and does not retain its content.
It is possible to enable cache profiling to analyze the performance of the cache for your program using the
ICACHECNF register. When profiling is enabled, the IHIT and IMISS registers are incremented for every
instruction cache hit or miss respectively. The hit and miss profiling registers do not wrap around after
reaching the maximum value. If the maximum value is reached, consider profiling for a shorter duration to get
correct numbers.
11.7 Registers
Table 12: Instances
Base address
Peripheral
Instance
Description
Configuration
0x4001E000
NVMC
NVMC
Non-Volatile Memory Controller
Table 13: Register Overview
Register
Offset
Description
READY
0x400
Ready flag
CONFIG
0x504
Configuration register
ERASEPAGE
0x508
Register for erasing a page in Code area
ERASEPCR1
0x508
Register for erasing a page in Code area. Equivalent to ERASEPAGE.
Deprecated
ERASEALL
0x50C
Register for erasing all non-volatile user memory
ERASEPCR0
0x510
Register for erasing a page in Code area. Equivalent to ERASEPAGE.
Deprecated
ERASEUICR
0x514
Register for erasing User Information Configuration Registers
ICACHECNF
0x540
I-Code cache configuration register.
IHIT
0x548
I-Code cache hit counter.
IMISS
0x54C
I-Code cache miss counter.
11.7.1 READY
Address offset: 0x400
Ready flag