Product Specs

33 TWIM — I
2
C compatible two-wire interface
master with EasyDMA
Page
307
#define BUFFER_SIZE 4
typedef struct ArrayList
{
uint8_t buffer[BUFFER_SIZE];
} ArrayList_type;
ArrayList_type MyArrayList[3];
//replace 'Channel' below by the specific data channel you want to use,
// for instance 'NRF_SPIM->RXD', 'NRF_TWIM->RXD', etc.
Channel.MAXCNT = BUFFER_SIZE;
Channel.PTR = &MyArrayList;
The Channel.MAXCNT register cannot be specified larger than the actual size of the buffer. If
Channel.MAXCNT is specified larger than the size of the buffer, the EasyDMA channel may overflow the
buffer.
This array list does not provide a mechanism to explicitly specify where the next item in the list is located.
Instead, it assumes that the list is organized as a linear array where items are located one after the other in
RAM.
Channel.PTR = &MyArrayList
Note: addresses are
assuming that
sizeof(buffer[n]) is one byte
0x20000000 : MyArrayList[0]
0x20000004 : MyArrayList[1]
0x20000008 : MyArrayList[2]
Figure 79: EasyDMA array list
33.3 Master write sequence
A TWI master write sequence is started by triggering the STARTTX task. After the STARTTX task has
been triggered, the TWI master will generate a start condition on the TWI bus, followed by clocking out the
address and the READ/WRITE bit set to 0 (WRITE=0, READ=1).
The address must match the address of the slave device that the master wants to write to. The READ/
WRITE bit is followed by an ACK/NACK bit (ACK=0 or NACK=1) generated by the slave.
After receiving the ACK bit, the TWI master will clock out the data bytes found in the transmit buffer located
in RAM at the address specified in the TXD.PTR register. Each byte clocked out from the master will be
followed by an ACK/NACK bit clocked in from the slave.
A typical TWI master write sequence is illustrated in Figure 80: TWI master writing data to a slave on page
308. Occurrence 2 in the figure illustrates clock stretching performed by the TWI master following a
SUSPEND task.
A SUSPENDED event indicates that the SUSPEND task has taken effect; this event can be used to
synchronize the software.
buffer[0]
buffer[1]
buffer[2]
buffer[3]
buffer[0]
buffer[1]
buffer[2]
buffer[3]
buffer[0]
buffer[1]
buffer[2]
buffer[3]