Product Specs

34 TWIS — I
2
C compatible two-wire interface
slave with EasyDMA
Page
321
34.1 Shared resources
The TWI slave shares registers and other resources with other peripherals that have the same ID as the TWI
slave.
Therefore, you must disable all peripherals that have the same ID as the TWI slave before the TWI slave can
be configured and used. Disabling a peripheral that has the same ID as the TWI slave will not reset any of
the registers that are shared with the TWI slave. It is therefore important to configure all relevant registers
explicitly to secure that the TWI slave operates correctly.
The Instantiation table in Instantiation on page 24 shows which peripherals have the same ID as the TWI
slave.
34.2 EasyDMA
The TWI slave implements EasyDMA for reading and writing to and from the RAM.
The STOPPED event indicates that EasyDMA has finished accessing the buffer in RAM.
If the TXD.PTR and the RXD.PTR are not pointing to the Data RAM region, an EasyDMA transfer may result
in a HardFault or RAM corruption. See Memory on page 23 for more information about the different memory
regions.
34.3 TWI slave responding to a read command
Before the TWI slave can respond to a read command the TWI slave must be configured correctly and
enabled via the ENABLE register. When enabled the TWI slave will be in its IDLE state where it will consume
I
IDLE
.
A read command is started when the TWI master generates a start condition on the TWI bus, followed by
clocking out the address and the READ/WRITE bit set to 1 (WRITE=0, READ=1). The READ/WRITE bit is
followed by an ACK/NACK bit (ACK=0 or NACK=1) response from the TWI slave.
The TWI slave is able to listen for up to two addresses at the same time. Which addresses to listen for is
configured in the ADDRESS registers and the CONFIG register.
The TWI slave will only acknowledge (ACK) the read command if the address presented by the master
matches one of the addresses the slave is configured to listen for. The TWI slave will generate a READ
event when it acknowledges the read command.
The TWI slave is only able to detect a read command from the IDLE state.
The TWI slave will set an internal 'TX prepared' flag when the PREPARETX task is triggered.
When the read command is received the TWI slave will enter the TX state if the internal 'TX prepared' flag is
set.
If the internal 'TX prepared' flag is not set when the read command is received, the TWI slave will stretch the
master's clock until the PREPARETX task is triggered and the internal 'TX prepared' flag is set.
The TWI slave will generate the TXSTARTED event and clear the 'TX prepared' flag ('unprepare TX') when
it enters the TX state. In this state the TWI slave will send the data bytes found in the transmit buffer to the
master using the master's clock. The TWI slave will consume I
TX
in this mode.
The TWI slave will go back to the IDLE state if the TWI slave receives a restart command when it is in the TX
state.
The TWI slave is stopped when it receives the stop condition from the TWI master. A STOPPED event will
be generated when the transaction has stopped. The TWI slave will clear the 'TX prepared' flag ('unprepare
TX') and go back to the IDLE state when it has stopped.
The transmit buffer is located in RAM at the address specified in the TXD.PTR register. The TWI slave will
only be able to send TXD.MAXCNT bytes from the transmit buffer for each transaction. If the TWI master