Product Specs

35 UARTE — Universal asynchronous receiver/
transmitter with EasyDMA
Page
336
To make sure that all data in the RX FIFO is moved to the RX buffer, the RXD.MAXCNT register must be set
to RXD.MAXCNT > 4, see Figure 96: UARTE reception with forced stop via STOPRX on page 336. The
UARTE will generate the ENDRX event after completing the FLUSHRX task even if the RX FIFO was empty
or if the RX buffer does not get filled up. To be able to know how many bytes have actually been received
into the RX buffer in this case, the CPU can read the RXD.AMOUNT register following the ENDRX event.
Figure 96: UARTE reception with forced stop via STOPRX
If HW flow control is enabled the RTS signal will be deactivated when the receiver is stopped via the
STOPRX task or when the UARTE is only able to receive four more bytes in its internal RX FIFO.
With flow control disabled, the UARTE will function in the same way as when the flow control is enabled
except that the RTS line will not be used. This means that no signal will be generated when the UARTE has
reached the point where it is only able to receive four more bytes in its internal RX FIFO. Data received when
the internal RX FIFO is filled up, will be lost.
The UARTE receiver will be in its lowest activity level, and consume the least amount of energy, when it is
stopped, i.e. before it is started via STARTRX or after it has been stopped via STOPRX and the RXTO event
has been generated. See POWER — Power supply on page 78 for more information about power modes.
35.5 Error conditions
An ERROR event, in the form of a framing error, will be generated if a valid stop bit is not detected in a
frame. Another ERROR event, in the form of a break condition, will be generated if the RXD line is held
active low for longer than the length of a data frame. Effectively, a framing error is always generated before a
break condition occurs.
An ERROR event will not stop reception. If the error was a parity error, the received byte will still be
transferred into Data RAM, and so will following incoming bytes. If there was a framing error (wrong stop bit),
that specific byte will NOT be stored into Data RAM, but following incoming bytes will.
35.6 Using the UARTE without flow control
If flow control is not enabled, the interface will behave as if the CTS and RTS lines are kept active all the
time.
35.7 Parity configuration
When parity is enabled, the parity will be generated automatically from the even parity of TXD and RXD for
transmission and reception respectively.
35.8 Low power
When putting the system in low power and the peripheral is not needed, lowest possible power consumption
is achieved by stopping, and then disabling the peripheral.
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Timeout
Lifeline
RXD
EasyDMA
ENDRX_STARTRX = 1
RXD.PTR = A
RXD.MAXCNT = 5
STARTRX
RXD.PTR = B
RXSTARTED
STARTRX
ENDRX
RXD.PTR = C
RXSTARTED
ENDRX_STARTRX = 0
STOPRX
ENDRX
RXTO
ENDRX
FLUSHRX