Product Specs

35 UARTE — Universal asynchronous receiver/
transmitter with EasyDMA
Page
345
Bit number
31 30
29
28
27
26
25
24
23 22 21 20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Id
A A
A
A
A
A
A
A
A A A A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Reset 0x00000000
0 0
0
0
0
0
0
0
0 0 0 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Id
RW Field
Value Id
Value
Description
A RW PTR Data pointer
35.10.16 TXD.MAXCNT
Address offset: 0x548
Maximum number of bytes in transmit buffer
Bit number
Id
Reset 0x00000000
31 30
0 0
29
0
28
0
27
0
26
0
25
0
24
0
23 22 21 20
0 0 0 0
19
0
18
0
17
0
16
0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
A
0
6
A
0
5
A
0
4
A
0
3
A
0
2
A
0
1
A
0
0
A
0
Id RW Field
Value Id
Value
Description
A RW MAXCNT Maximum number of bytes in transmit buffer
35.10.17 TXD.AMOUNT
Address offset: 0x54C
Number of bytes transferred in the last transaction
Bit number
Id
Reset 0x00000000
31 30
0 0
29
0
28
0
27
0
26
0
25
0
24
0
23 22 21 20
0 0 0 0
19
0
18
0
17
0
16
0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
A
0
6
A
0
5
A
0
4
A
0
3
A
0
2
A
0
1
A
0
0
A
0
Id RW Field
Value Id
Value
Description
A R AMOUNT Number of bytes transferred in the last transaction
35.10.18 CONFIG
Address offset: 0x56C
Configuration of parity and hardware flow control
Bit number
Id
Reset 0x00000000
31 30
0 0
29
0
28
0
27
0
26
0
25
0
24
0
23 22 21 20
0 0 0 0
19
0
18
0
17
0
16
0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
B
0
2
B
0
1
B
0
0
A
0
Id RW Field
Value Id
Value
Description
A RW HWFC
Disabled
0
Hardware flow control
Disabled
Enabled
1
Enabled
B RW PARITY
Excluded
0x0
Parity
Exclude parity bit
Included
0x7
Include parity bit
35.11 Electrical specification
35.11.1 UARTE electrical specification
Symbol
Description
Min.
Typ.
Max.
Units
f
UARTE
Baud rate for UARTE
32
.
1000
kbps
I
UARTE1M
Run current at max baud rate.
55
µA
I
UARTE115k
Run current at 115200 bps.
55
µA
I
UARTE1k2
Run current at 1200 bps.
55
µA
I
UARTE,IDLE
Idle current for UARTE (STARTed, no XXX activity)
1
µA
t
UARTE,CTSH
CTS high time
1
µs
32
Higher baud rates may require GPIOs to be set as High Drive, see GPIO chapter for more details.