Product Specs

36 QDEC — Quadrature decoder
Page
354
Bit number
31 30
29
28
27
26
25
24
23 22 21 20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Id
A A
A
A
A
A
A
A
A A A A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Reset 0x00000000
0 0
0
0
0
0
0
0
0 0 0 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Id
RW Field
Value Id
Value
Description
The value is a 2's complement value, and the sign gives the
direction of the motion. The value '2' indicates a double
transition.
36.7.8 REPORTPER
Address offset: 0x510
Number of samples to be taken before REPORTRDY and DBLRDY events can be generated
Bit number
Id
Reset 0x00000000
31 30
0 0
29
0
28
0
27
0
26
0
25
0
24
0
23 22 21 20
0 0 0 0
19
0
18
0
17
0
16
0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
A
0
2
A
0
1
A
0
0
A
0
Id RW Field
Value Id
Value
Description
A RW REPORTPER
Specifies the number of samples to be accumulated in the ACC
register before the REPORTRDY and DBLRDY events can be
generated
The report period in [us] is given as: RPUS = SP * RP Where
RPUS is the report period in [us/report], SP is the sample period
in [us/sample] specified in SAMPLEPER, and RP is the report
period in [samples/report] specified in REPORTPER .
10Smpl
0
10 samples / report
40Smpl
1
40 samples / report
80Smpl
2
80 samples / report
120Smpl
3
120 samples / report
160Smpl
4
160 samples / report
200Smpl
5
200 samples / report
240Smpl
6
240 samples / report
280Smpl
7
280 samples / report
1Smpl
8
1 sample / report
36.7.9 ACC
Address offset: 0x514
Register accumulating the valid transitions
Bit number
31 30
29
28
27
26
25
24
23 22 21 20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Id
A A
A
A
A
A
A
A
A A A A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Reset 0x00000000
0 0
0
0
0
0
0
0
0 0 0 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Id
RW Field
Value Id
Value
Description
A R ACC
36.7.10 ACCREAD
Address offset: 0x518
Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task
[-1024..1023]
Register accumulating all valid samples (not double transition)
read from the SAMPLE register
Double transitions ( SAMPLE = 2 ) will not be accumulated in
this register. The value is a 32 bit 2's complement value. If a
sample that would cause this register to overflow or underflow
is received, the sample will be ignored and an overflow event
( ACCOF ) will be generated. The ACC register is cleared by
triggering the READCLRACC or the RDCLRACC task.