Product Specs

37 SAADC — Successive approximation analog-
to-digital converter
Page
359
The ADC has a wide selection of gains controlled in the GAIN field of the CH[n].CONFIG register. If
CH[n].CONFIG.REFSEL=0, the input range of the ADC core is nominally ±0.6 V differential and the input
must be scaled accordingly.
The ADC has a temperature dependent offset. If the ADC is to operate over a large temperature range, we
recommend running CALIBRATEOFFSET at regular intervals, a CALIBRATEDONE event will be fired when
the calibration is complete
37.4 Analog inputs and channels
Up to eight analog input channels, CH[n](n=0..7), can be configured.
See Shared resources on page 357 for shared input with comparators.
Any one of the available channels can be enabled for the ADC to operate in one-shot mode. If more than
one CH[n] is configured, the ADC enters scan mode.
An analog input is selected as a positive converter input if CH[n].PSELP is set, setting CH[n].PSELP also
enables the particular channel.
An analog input is selected as a negative converter input if CH[n].PSELN is set. The CH[n].PSELN register
will have no effect unless differential mode is enabled, see MODE field in CH[n].CONFIG register.
If more than one of the CH[n].PSELP registers is set, the device enters scan mode. Input selections in scan
mode are controlled by the CH[n].PSELP and CH[n].PSELN registers, where CH[n].PSELN is only used if
the particular scan channel is specified as differential, see MODE field in CH[n].CONFIG register.
Important: Channels selected for either COMP or LPCOMP cannot be used at the same time for
ADC sampling, though channels not selected for use by these blocks can be used by the ADC.
Table 87: Legal connectivity CH[n] vs. analog input
Channel input
Source
Connectivity
CH[n].PSELP
AIN0…AIN7
Yes(any)
CH[n].PSELP
VDD
Yes
CH[n].PSELN
AIN0…AIN7
Yes(any)
CH[n].PSELN
VDD
Yes
37.5 Operation modes
The ADC input configuration supports one-shot mode, continuous mode and scan mode.
Scan mode and oversampling cannot be combined.
37.5.1 One-shot mode
One-shot operation is configured by enabling only one of the available channels defined by CH[n].PSELP,
CH[n].PSELN, and CH[n].CONFIG registers.
Upon a SAMPLE task, the ADC starts to sample the input voltage. The CH[n].CONFIG.TACQ controls the
acquisition time.
A DONE event signals that one sample has been taken.
In this mode, the RESULTDONE event has the same meaning as DONE when no oversampling takes place.
Note that both events may occur before the actual value has been transferred into RAM by EasyDMA. For
more information, see EasyDMA on page 361.
37.5.2 Continuous mode
Continuous sampling can be achieved by using the internal timer in the ADC, or triggering the SAMPLE task
from one of the general purpose timers through the PPI.
Care shall be taken to ensure that the sample rate fulfils the following criteria, depending on how many
channels are active:
f
SAMPLE
< 1/[t
ACQ
+ t
conv
]