Product Specs

37 SAADC — Successive approximation analog-
to-digital converter
Page
373
Bit number
Id
Reset 0x00000000
31 30
0 0
29
0
28
0
27
0
26
0
25
0
24
0
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8
V U T S R Q P O N M L K J I
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
7
H
0
6
G
0
5
F
0
4
E
0
3
D
0
2
C
0
1
B
0
0
A
0
Id RW Field
Value Id
Value
Description
V RW CH7LIMITL
Write '1' to Disable interrupt for CH[7].LIMITL event
See EVENTS_CH[7].LIMITL
Clear
1
Disable
Disabled
0
Read: Disabled
Enabled
1
Read: Enabled
37.11.4 STATUS
Address offset: 0x400
Status
Bit number
Id
Reset 0x00000000
31 30
0 0
29
0
28
0
27
0
26
0
25
0
24
0
23 22 21 20
0 0 0 0
19
0
18
0
17
0
16
0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
A
0
Id RW Field
Value Id
Value
Description
A R STATUS Status
Ready 0 ADC is ready. No on-going conversion.
Busy 1 ADC is busy. Conversion in progress.
37.11.5 ENABLE
Address offset: 0x500
Enable or disable ADC
Bit number
Id
Reset 0x00000000
31 30
0 0
29
0
28
0
27
0
26
0
25
0
24
0
23 22 21 20
0 0 0 0
19
0
18
0
17
0
16
0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
A
0
Id RW Field
Value Id
Value
Description
A RW ENABLE
Disabled
0
Enable or disable ADC
Disable ADC
Enabled
1
Enable ADC
When enabled, the ADC will acquire access to the analog input
pins specified in the CH[n].PSELP and CH[n].PSELN registers.
37.11.6 CH[0].PSELP
Address offset: 0x510
Input positive pin selection for CH[0]
Bit number
Id
Reset 0x00000000
31 30
0 0
29
0
28
0
27
0
26
0
25
0
24
0
23 22 21 20
0 0 0 0
19
0
18
0
17
0
16
0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
A
0
3
A
0
2
A
0
1
A
0
0
A
0
Id RW Field
Value Id
Value
Description
A RW PSELP
Analog positive input channel
NC
0
Not connected
AnalogInput0
1
AIN0
AnalogInput1
2
AIN1
AnalogInput2
3
AIN2
AnalogInput3
4
AIN3
AnalogInput4
5
AIN4
AnalogInput5
6
AIN5
AnalogInput6
7
AIN6
AnalogInput7
8
AIN7
VDD
9
VDD