Product Specs

37 SAADC — Successive approximation analog-
to-digital converter
Page
378
Bit number
Id
Reset 0x00000000
31 30
0 0
29
0
28
0
27
0
26
0
25
0
24
0
23 22 21 20
0 0 0 0
19
0
18
0
17
0
16
0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
A
0
3
A
0
2
A
0
1
A
0
0
A
0
Id RW Field
Value Id
Value
Description
VDD 9 VDD
37.11.16 CH[2].CONFIG
Address offset: 0x538
Input configuration for CH[2]
Bit number
Id
Reset 0x00020000
31 30
0 0
29
0
28
0
27
0
26
0
25
0
24
G
0
23 22 21 20
F
0 0 0 0
19
0
18
E
0
17
E
1
16
E
0
15
0
14
0
13
0
12
D
0
11
0
10
C
0
9
C
0
8
C
0
7
0
6
0
5
B
0
4
B
0
3
0
2
0
1
A
0
0
A
0
Id RW Field
Value Id
Value
Description
A
RW
RESP
Positive channel resistor control
Bypass
0
Bypass resistor ladder
Pulldown
1
Pull-down to GND
Pullup
2
Pull-up to VDD
VDD1_2
3
Set input at VDD/2
B
RW
RESN
Negative channel resistor control
Bypass
0
Bypass resistor ladder
Pulldown
1
Pull-down to GND
Pullup
2
Pull-up to VDD
VDD1_2
3
Set input at VDD/2
C
RW
GAIN
Gain control
Gain1_6
0
1/6
Gain1_5
1
1/5
Gain1_4
2
1/4
Gain1_3
3
1/3
Gain1_2
4
1/2
Gain1
5
1
Gain2
6
2
Gain4
7
4
D
RW
REFSEL
Reference control
Internal
0
Internal reference (0.6 V)
VDD1_4
1
VDD/4 as reference
E
RW
TACQ
Acquisition time, the time the ADC uses to sample the input
voltage
3us
0
3 us
5us
1
5 us
10us
2
10 us
15us
3
15 us
20us
4
20 us
40us
5
40 us
F
RW
MODE
Enable differential mode
SE
0
Single ended, PSELN will be ignored, negative input to ADC
shorted to GND
Diff
1
Differential
G
RW
BURST
Enable burst mode
Disabled
0
Burst mode is disabled (normal operation)
Enabled
1
Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of
samples as fast as it can, and sends the average to Data RAM.
37.11.17 CH[2].LIMIT
Address offset: 0x53C
High/low limits for event monitoring a channel