Product Specs

37 SAADC — Successive approximation analog-
to-digital converter
Page
384
Bit number
Id
Reset 0x00020000
31 30
0 0
29
0
28
0
27
0
26
0
25
0
24
G
0
23 22 21 20 19 18
F E
0 0 0 0 0 0
17
E
1
16
E
0
15
0
14
0
13
0
12
D
0
11
0
10
C
0
9
C
0
8
C
0
7
0
6
0
5
B
0
4
B
0
3
0
2
0
1
A
0
0
A
0
Id RW Field
Value Id
Value
Description
VDD1_4
1
VDD/4 as reference
E
RW
TACQ
Acquisition time, the time the ADC uses to sample the input
voltage
3us
0
3 us
5us
1
5 us
10us
2
10 us
15us
3
15 us
20us
4
20 us
40us
5
40 us
F
RW
MODE
SE
Diff
0
1
Enable differential mode
Single ended, PSELN will be ignored, negative input to ADC
shorted to GND
Differential
G
RW
BURST
Enable burst mode
Disabled
0
Burst mode is disabled (normal operation)
Enabled
1
Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of
samples as fast as it can, and sends the average to Data RAM.
37.11.29 CH[5].LIMIT
Address offset: 0x56C
High/low limits for event monitoring a channel
Bit number
31 30
29
28
27
26
25
24
23 22 21 20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Id
B B
B
B
B
B
B
B
B B B B
B
B
B
B
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Reset 0x7FFF8000
0 1
1
1
1
1
1
1
1 1 1 1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Id
RW Field
Value Id
Value
Description
A RW LOW
[-32768 to +32767]
Low level limit
B RW HIGH
[-32768 to +32767]
High level limit
37.11.30 CH[6].PSELP
Address offset: 0x570
Input positive pin selection for CH[6]
Bit number
Id
Reset 0x00000000
31 30
0 0
29
0
28
0
27
0
26
0
25
0
24
0
23 22 21 20
0 0 0 0
19
0
18
0
17
0
16
0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
A
0
3
A
0
2
A
0
1
A
0
0
A
0
Id RW Field
Value Id
Value
Description
A RW PSELP
Analog positive input channel
NC
0
Not connected
AnalogInput0
1
AIN0
AnalogInput1
2
AIN1
AnalogInput2
3
AIN2
AnalogInput3
4
AIN3
AnalogInput4
5
AIN4
AnalogInput5
6
AIN5
AnalogInput6
7
AIN6
AnalogInput7
8
AIN7
VDD
9
VDD
37.11.31 CH[6].PSELN
Address offset: 0x574
Input negative pin selection for CH[6]