Product Specs

37 SAADC — Successive approximation analog-
to-digital converter
Page
391
Figure 107: ADC DNL vs Output Code
Figure 108: FFT of a 2.8 kHz sine at 200 ksps ()
37.13 Performance factors
Clock jitter, affecting sample timing accuracy, and circuit noise can affect ADC performance.
Jitter can be between START tasks or from START task to acquisition. START timer accuracy and startup
times of regulators and references will contribute to variability. Sources of circuit noise may include CPU
activity and the DC/DC regulator. Best ADC performance is achieved using START timing based on the
TIMER module, HFXO clock source, and Constant Latency mode.
2
1.5
1
0.5
0
-0.5
-1
-1.5
-2
0 64 128 192 256 320 384 448 512 576 640 704 768 832 896 960
Output code
Magnitu de [dBFS]
0
-20
12-bit resolution
Differential mode
Internal reference
200kHz sampling frequency
3µs aquisition time
4096 point FFT (EasyDMA)
SNDR = 56.6 dB
ENOB = 9.1 bit
SFDR = 72 dBc
-40
-60
-80
-100
-120
0
10
20
30
40
50
Frequency [kHz]
60
70
80
90
100
DNL [LSB10b]