Product Specs

40 WDT — Watchdog timer
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timeout [s] = ( CRV + 1 ) / 32768
40 WDT — Watchdog timer
A countdown watchdog timer using the low-frequency clock source (LFCLK) offers configurable and robust
protection against application lock-up.
The watchdog timer is started by triggering the START task.
The watchdog can be paused during long CPU sleep periods for low power applications and when the
debugger has halted the CPU. The watchdog is implemented as a down-counter that generates a TIMEOUT
event when it wraps over after counting down to 0. When the watchdog timer is started through the START
task, the watchdog counter is loaded with the value specified in the CRV register. This counter is also
reloaded with the value specified in the CRV register when a reload request is granted.
The watchdog’s timeout period is given by:
When started, the watchdog will automatically force the 32.768 kHz RC oscillator on as long as no other
32.768 kHz clock source is running and generating the 32.768 kHz system clock, see chapter CLOCK —
Clock control on page 101.
40.1 Reload criteria
The watchdog has eight separate reload request registers, which shall be used to request the watchdog to
reload its counter with the value specified in the CRV register. To reload the watchdog counter, the special
value 0x6E524635 needs to be written to all enabled reload registers.
One or more RR registers can be individually enabled through the RREN register.
40.2 Temporarily pausing the watchdog
By default, the watchdog will be active counting down the down-counter while the CPU is sleeping and when
it is halted by the debugger. It is however possible to configure the watchdog to automatically pause while
the CPU is sleeping as well as when it is halted by the debugger.
40.3 Watchdog reset
A TIMEOUT event will automatically lead to a watchdog reset.
See Reset on page 82 for more information about reset sources. If the watchdog is configured to generate
an interrupt on the TIMEOUT event, the watchdog reset will be postponed with two 32.768 kHz clock
cycles after the TIMEOUT event has been generated. Once the TIMEOUT event has been generated, the
impending watchdog reset will always be effectuated.
The watchdog must be configured before it is started. After it is started, the watchdog’s configuration
registers, which comprise registers CRV, RREN, and CONFIG, will be blocked for further configuration.
The watchdog can be reset from several reset sources, see Reset behavior on page 83.
When the device starts running again, after a reset, or waking up from OFF mode, the watchdog
configuration registers will be available for configuration again.