Product Specs
Table Of Contents
- 1Revision history
- 2About this document
- 3Block diagram
- 4Pin assignments
- 5Absolute maximum ratings
- 6Recommended operating conditions
- 7CPU
- 8Memory
- 9AHB multilayer
- 10EasyDMA
- 11NVMC — Non-volatile memory controller
- 12BPROT — Block protection
- 13FICR — Factory information configuration registers
- 14UICR — User information configuration registers
- 14.1Registers
- Table 18: Instances
- 14.1.2NRFFW[1]
- 14.1.3NRFFW[2]
- 14.1.4NRFFW[3]
- 14.1.5NRFFW[4]
- 14.1.6NRFFW[5]
- 14.1.7NRFFW[6]
- 14.1.8NRFFW[7]
- 14.1.9NRFFW[8]
- 14.1.10NRFFW[9]
- 14.1.11NRFFW[10]
- 14.1.12NRFFW[11]
- 14.1.13NRFFW[12]
- 14.1.14NRFFW[13]
- 14.1.15NRFFW[14]
- 14.1.16NRFHW[0]
- 14.1.17NRFHW[1]
- 14.1.18NRFHW[2]
- 14.1.19NRFHW[3]
- 14.1.20NRFHW[4]
- 14.1.21NRFHW[5]
- 14.1.22NRFHW[6]
- 14.1.23NRFHW[7]
- 14.1.24NRFHW[8]
- 14.1.25NRFHW[9]
- 14.1.26NRFHW[10]
- 14.1.27NRFHW[11]
- 14.1.60PSELRESET[0]
- 14.1.61PSELRESET[1]
- 14.1.63NFCPINS
- 14.1Registers
- 15Peripheral interface
- 16Debug and trace
- 17Power and clock management
- 18POWER — Power supply
- 18.1Regulators
- 18.2System OFF mode
- 18.3System ON mode
- 18.4Power supply supervisor
- 18.5RAM sections
- 18.6Reset
- 18.7Retained registers
- 18.8Reset behavior
- 18.9Registers
- Table 23: Instances
- 18.9.6POFCON
- 18.9.7GPREGRET
- 18.9.8GPREGRET2
- 18.9.9RAMON ( Deprecated )
- 18.9.10RAMONB ( Deprecated )
- 18.9.12RAM[0].POWER
- 18.9.13RAM[0].POWERSET
- 18.9.14RAM[0].POWERCLR
- 18.9.15RAM[1].POWER
- 18.9.16RAM[1].POWERSET
- 18.9.17RAM[1].POWERCLR
- 18.9.18RAM[2].POWER
- 18.9.19RAM[2].POWERSET
- 18.9.20RAM[2].POWERCLR
- 18.9.21RAM[3].POWER
- 18.9.22RAM[3].POWERSET
- 18.9.23RAM[3].POWERCLR
- 18.9.24RAM[4].POWER
- 18.9.25RAM[4].POWERSET
- 18.9.26RAM[4].POWERCLR
- 18.9.27RAM[5].POWER
- 18.9.28RAM[5].POWERSET
- 18.9.29RAM[5].POWERCLR
- 18.9.30RAM[6].POWER
- 18.9.31RAM[6].POWERSET
- 18.9.32RAM[6].POWERCLR
- 18.9.33RAM[7].POWER
- 18.9.34RAM[7].POWERSET
- 18.9.35RAM[7].POWERCLR
- 18.10Electrical specification
- 19CLOCK — Clock control
- 20GPIO — General purpose input/output
- 21GPIOTE — GPIO tasks and events
- 22PPI — Programmable peripheral interconnect
- 23RADIO — 2.4 GHz Radio
- Figure 29: RADIO block diagram
- 23.1EasyDMA
- 23.2Packet configuration
- 23.3Maximum packet length
- 23.4Address configuration
- 23.5Data whitening
- 23.6CRC
- 23.7Radio states
- 23.8Transmit sequence
- 23.9Receive sequence
- 23.10Received Signal Strength Indicator (RSSI)
- 23.11Interframe spacing
- 23.12Device address match
- 23.13Bit counter
- 23.14Registers
- 23.15Electrical specification
- 24TIMER — Timer/counter
- 25RTC — Real-time counter
- 26RNG — Random number generator
- 27TEMP — Temperature sensor
- 28ECB — AES electronic codebook mode encryption
- 29CCM — AES CCM mode encryption
- Figure 59: Key-stream generation followed by encry
- 29.1Shared resources
- 29.2Encryption
- 29.3Decryption
- 29.4AES CCM and RADIO concurrent operation
- 29.5Encrypting packets on-the-fly in radio transmit mo
- 29.6Decrypting packets on-the-fly in radio receive mod
- 29.7CCM data structure
- 29.8EasyDMA and ERROR event
- 29.9Registers
- 30AAR — Accelerated address resolver
- 31SPIM — Serial peripheral interface master with Eas
- 32SPIS — Serial peripheral interface slave with Easy
- Figure 73: SPI slave
- 32.1Shared resources
- 32.2EasyDMA
- 32.3SPI slave operation
- 32.4Pin configuration
- 32.5Registers
- Table 71: Instances
- 32.5.8PSELMISO ( Deprecated )
- 32.5.9PSELMOSI ( Deprecated )
- 32.5.10PSELCSN ( Deprecated )
- 32.5.13PSEL.MOSI
- 32.5.15RXDPTR ( Deprecated )
- 32.5.16MAXRX ( Deprecated )
- 32.5.17AMOUNTRX ( Deprecated )
- 32.5.19RXD.MAXCNT
- 32.5.20RXD.AMOUNT
- 32.5.21TXDPTR ( Deprecated )
- 32.5.22MAXTX ( Deprecated )
- 32.5.23AMOUNTTX ( Deprecated )
- 32.5.25TXD.MAXCNT
- 32.5.26TXD.AMOUNT
- 32.5.28DEF
- 32.6Electrical specification
- 33TWIM — I2C compatible two-wire interface master wi
- 34TWIS — I2C compatible two-wire interface slave wit
- Figure 86: TWI slave with EasyDMA
- Figure 87: A typical TWI setup comprising one mast
- Figure 88: TWI slave state machine
- 34.1Shared resources
- 34.2EasyDMA
- 34.3TWI slave responding to a read command
- 34.4TWI slave responding to a write command
- 34.5Master repeated start sequence
- 34.6Terminating an ongoing TWI transaction
- 34.7Low power
- 34.8Slave mode pin configuration
- 34.9Registers
- 34.10Electrical specification
- 35UARTE — Universal asynchronous receiver/ transmitt
- 36QDEC — Quadrature decoder
- 37SAADC — Successive approximation analog-to- digita
- 37.1Shared resources
- 37.2Overview
- 37.3Digital output
- 37.4Analog inputs and channels
- 37.5Operation modes
- 37.6EasyDMA
- 37.7Resistor ladder
- 37.8Reference
- 37.9Acquisition time
- 37.10Limits event monitoring
- 37.11Registers
- Table 89: Instances
- 37.11.7CH[0].PSELN
- 37.11.8CH[0].CONFIG
- 37.11.9CH[0].LIMIT
- 37.11.11CH[1].PSELN
- 37.11.12CH[1].CONFIG
- 37.11.13CH[1].LIMIT
- 37.11.15CH[2].PSELN
- 37.11.16CH[2].CONFIG
- 37.11.17CH[2].LIMIT
- 37.11.19CH[3].PSELN
- 37.11.20CH[3].CONFIG
- 37.11.21CH[3].LIMIT
- 37.11.23CH[4].PSELN
- 37.11.24CH[4].CONFIG
- 37.11.25CH[4].LIMIT
- 37.11.27CH[5].PSELN
- 37.11.28CH[5].CONFIG
- 37.11.29CH[5].LIMIT
- 37.11.31CH[6].PSELN
- 37.11.32CH[6].CONFIG
- 37.11.33CH[6].LIMIT
- 37.11.35CH[7].PSELN
- 37.11.36CH[7].CONFIG
- 37.11.37CH[7].LIMIT
- 37.11.39OVERSAMPLE
- 37.11.40SAMPLERATE
- 37.11.41RESULT.PTR
- 37.11.42RESULT.MAXCNT
- 37.11.43RESULT.AMOUNT
- 37.12Electrical specification
- 37.13Performance factors
- 38COMP — Comparator
- 39LPCOMP — Low power comparator
- 40WDT — Watchdog timer
- 41SWI — Software interrupts
- 42NFCT — Near field communication tag
- 42.1Overview
- 42.2Pin configuration
- 42.3EasyDMA
- 42.4Collision resolution
- 42.5Frame timing controller
- 42.6Frame assembler
- 42.7Frame disassembler
- 42.8Antenna interface
- 42.9NFCT antenna recommendations
- 42.10Battery protection
- 42.11References
- 42.12Registers
- Table 99: Instances
- 42.12.6FRAMESTATUS.RX
- 42.12.7CURRENTLOADCTRL
- 42.12.8FIELDPRESENT
- 42.12.9FRAMEDELAYMIN
- 42.12.10FRAMEDELAYMAX
- 42.12.11FRAMEDELAYMODE
- 42.12.12PACKETPTR
- 42.12.13MAXLEN
- 42.12.14TXD.FRAMECONFIG
- 42.12.15TXD.AMOUNT
- 42.12.16RXD.FRAMECONFIG
- 42.12.17RXD.AMOUNT
- 42.12.18NFCID1_LAST
- 42.12.19NFCID1_2ND_LAST
- 42.12.20NFCID1_3RD_LAST
- 42.12.21SENSRES
- 42.12.22SELRES
- 42.13Electrical specification
- 43PDM — Pulse density modulation interface
- 44I2S — Inter-IC sound interface
- 44.1Mode
- 44.2Transmitting and receiving
- 44.3Left right clock (LRCK)
- 44.4Serial clock (SCK)
- 44.5Master clock (MCK)
- 44.6Width, alignment and format
- 44.7EasyDMA
- 44.8Module operation
- 44.9Pin configuration
- 44.10Registers
- Table 108: Instances
- 44.10.7CONFIG.TXEN
- 44.10.8CONFIG.MCKEN
- 44.10.9CONFIG.MCKFREQ
- 44.10.10CONFIG.RATIO
- 44.10.11CONFIG.SWIDTH
- 44.10.12CONFIG.ALIGN
- 44.10.13CONFIG.FORMAT
- 44.10.14CONFIG.CHANNELS
- 44.10.15RXD.PTR
- 44.10.16TXD.PTR
- 44.10.17RXTXD.MAXCNT
- 44.10.18PSEL.MCK
- 44.10.20PSEL.LRCK
- 44.10.21PSEL.SDIN
- 44.10.22PSEL.SDOUT
- 44.11Electrical specification
- 45MWU — Memory watch unit
- Table 110: Memory regions
- 45.1Registers
- Table 111: Instances
- 45.1.4NMIEN
- 45.1.5NMIENSET
- 45.1.6NMIENCLR
- 45.1.7PERREGION[0].SUBSTATWA
- 45.1.8PERREGION[0].SUBSTATRA
- 45.1.9PERREGION[1].SUBSTATWA
- 45.1.10PERREGION[1].SUBSTATRA
- 45.1.12REGIONENSET
- 45.1.14REGION[0].START
- 45.1.15REGION[0].END
- 45.1.16REGION[1].START
- 45.1.17REGION[1].END
- 45.1.18REGION[2].START
- 45.1.19REGION[2].END
- 45.1.20REGION[3].START
- 45.1.21REGION[3].END
- 45.1.22PREGION[0].START
- 45.1.23PREGION[0].END
- 45.1.25PREGION[1].START
- 45.1.26PREGION[1].END
- 46EGU — Event generator unit
- 47PWM — Pulse width modulation
- 48SPI — Serial peripheral interface master
- 49TWI — I2C compatible two-wire interface
- 50UART — Universal asynchronous receiver/ transmitte
- 51Mechanical specifications
- 52Ordering information
- 53Reference circuitry
- 53.1Schematic QFAA and QFAB QFN48 with internal LDO se
- 53.2Schematic QFAA and QFAB QFN48 with DC/DC regulato
- 53.3Schematic QFAA and QFAB QFN48 with DC/DC regulato
- 53.4Schematic CIAA WLCSP with internal LDO setup
- 53.5Schematic CIAA WLCSP with DC/DC regulator setup
- 53.6Schematic CIAA WLCSP with DC/DC regulator and
- 53.7PCB guidelines
- 53.8PCB layout example
- 54Liability disclaimer
- Mouser Electronics
42 NFCT — Near field communication tag
Page
423
The Frame Assemble operation is illustrated in Figure 120: Frame assemble on page 423 for different
settings in TXD.FRAMECONFIG. All shaded bits fields are added by the frame assembler. Some of these
bits are optional and appearances are configured in TXD.FRAMECONFIG. Please note that the frames
illustrated do not necessarily comply with the NFC specification. The figure is only to illustrate the behavior of
the NFC peripheral.
Data from RAM
Byte 1: PACKETPTR + 0 Byte 2: PACKETPTR + 1
Byte (TXDATABYTES) Byte (TXDATABYTES + 1)
Frame on air
PARITY = Parity, TXDATABITS = 0, CRCM ODETX = CRC16TX
Byte 1 Byte 2
Byte (TXDATABYTES)
(only if TXDATABITS > 0)
C b
PARITY = Parity, TXDATABITS = 4, CRCMODETX = NoCRCTX, DISCARDMODE = DiscardStart
Byte 1 Byte 2 Byte (TXDATABYTES) Byte (TXDATABYTES + 1)
SoF
b4
b5
b6
b7
P
b0
b1
b2
b3
b4
b5
b6
b7
P
b0
b1
b2
b3
b4
b5
b6
b7
P
b0
b1
b2
b3
b4
b5
b6
b7
P
EoF
PARITY = Parity, TXDATABITS = 0, CRCMODETX = NoCRCTX
Byte 1 Byte TXDATABYTES
SoF
b0
b1
b2
b3
b4
b5
b6
b7
P
EoF
Figure 120: Frame assemble
The accurate timing for transmitting the frame on air is set using the frame timing controller settings.
42.7 Frame disassembler
The NFC peripheral implements a frame disassembler in hardware.
When the NFC peripheral is in the ACTIVE_A state, the software can decide to enter RX or TX mode. For
TX, see Frame assembler on page 422. For RX, the software must indicate the address of the destination
buffer in Data RAM and its size through programming the PACKETPTR and MAXCNT registers respectively,
then issuing a ENABLERXDATA task.
The STARTED event indicates that the PACKETPTR and MAXCNT registers have been captured by the
frame disassembler's EasyDMA.
When an incoming frame starts, the RXFRAMESTART event will get issued and data will be written to the
buffer in Data RAM. The frame disassembler will verify and remove on the fly any parity bits and SoF and
End of Frame (EoF) symbols based on RXD.FRAMECONFIG register configuration. It will, however, verify
and transfer the CRC bytes into RAM, if the CRC is was enabled through RXD.FRAMECONFIG.
When an EoF symbol is detected, the NFC peripheral will assert the RXFRAMEEND event and write the
RXD.AMOUNT register to indicate numbers of received bytes and bits in the data packet. The module does
not interpret the content of the data received from the remote NFC device, except for SoF, EoF, parity and
CRC checking, as described above. The Frame disassemble operation is illustrated in Figure 121: Frame
disassemble illustration on page 423.
Per NFC specification, the time between end of frame to the next start of frame can be as short as 86 µs,
so care must be taken that PACKETPTR and MAXCNT are ready and ENABLERXDATA is issued on time
after the end of previous frame. The use of a PPI shortcut from TXFRAMEEND to ENABLERXDATA is
recommended.
Frame on air
PARITY = Parity, RXDATABITS = 0, CRCMODERX = CRC16RX, RXDATABITS = 0
Byte 1
Byte 2 Byte RXDATABYTES
C b
PARITY = Parity, CRCMODERX = NoCRCRX, RXDATABITS = 4
Byte 1 Byte 2 Byte RXDATABYTES Byte (RXDATABYTES+1)
SoF
b0
b1
b2
b3
b4
b5
b6
b7
P
b0
b1
b2
b3
b4
b5
b6
b7
P
b0
b1
b2
b3
b4
b5
b6
b7
P
b0
b1
b2
b3
EoF
PARITY = NoParity, CRCMODERX = NoCRCRX, RXDATABITS = 0
Byte 1 Byte 2
Byte RXDATABYTES
SoF
b0
b1
b2
b3
b4
b5
b6
b7
b0
b1
b2
b3
b4
b5
b6
b7
b0
b1
b2
b3
b4
b5
b6
b7
b0
b1
b2
b3
b4
b5
b6
b7
EoF
Data to RAM
Byte 1: (PACKETPTR + 0) Byte 2: (PACKETPTR + 1) Byte RXDATABYTES Byte (RXDATABYTES+1)
Figure 121: Frame disassemble illustration
(only if RXDATABITS > 0)
b0
b1
b2
b3
b4
b5
b6
b7
b0
b1
b2
b3
b4
b5
b6
b7
P
b7
b6
b5
b4
b3
b2
b1
b0
b0
b1
b2
b3
b4
b5
b6
b7
b0
b1
b2
b3
b4
b5
b6
b7
SoF
b0
b1
b2
b3
b4
b5
b6
b7
P
b0
b1
b2
b3
b4
b5
b6
b7
P
b0
b1
b2
b3
b4
b5
b6
b7
P
CRC
1 (8 b
it)
P
CR
2 (8
it)
P
EoF
SoF
b0
b1
b2
b3
b4
b5
b6
b7
P
b0
b1
b2
b3
b4
b5
b6
b7
P
b0
b1
b2
b3
b4
b5
b6
b7
P
CRC
1 (8 b
it)
P
CR
2 (8
it)
P
EoF
b0
b1
b2
b3
b4
b5
b6
b7
b0
b1
b2
b3
b4
b5
b6
b7
b0
b1
b2
b3
b4
b5
b6
b7
b0
b1
b2
b3
b4
b5
b6
b7










