Product Specs

43 PDM — Pulse density modulation interface
Page
443
43.7.7 GAINL
Address offset: 0x518
Left output gain adjustment
Bit number
Id
Reset 0x00000028
31 30
0 0
29
0
28
0
27
0
26
0
25
0
24
0
23 22 21 20
0 0 0 0
19
0
18
0
17
0
16
0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
A
0
5
A
1
4
A
0
3
A
1
2
A
0
1
A
0
0
A
0
Id RW Field
Value Id
Value
Description
A RW GAINL
Left output gain adjustment, in 0.5 dB steps, around the default
module gain (see electrical parameters)
0x00 -20 dB gain adjust
0x01 -19.5 dB gain adjust
(...)
0x27 -0.5 dB gain adjust
0x28 0 dB gain adjust
0x29 +0.5 dB gain adjust
(...)
0x4F +19.5 dB gain adjust
0x50 +20 dB gain adjust
MinGain
0x00
-20dB gain adjustment (minimum)
DefaultGain
0x28
0dB gain adjustment ('2500 RMS' requirement)
MaxGain
0x50
+20dB gain adjustment (maximum)
43.7.8 GAINR
Address offset: 0x51C
Right output gain adjustment
Bit number
Id
Reset 0x00000028
31 30
0 0
29
0
28
0
27
0
26
0
25
0
24
0
23 22 21 20
0 0 0 0
19
0
18
0
17
0
16
0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
A
0
6
A
0
5
A
1
4
A
0
3
A
1
2
A
0
1
A
0
0
A
0
Id RW Field
Value Id
Value
Description
A RW GAINR
Right output gain adjustment, in 0.5 dB steps, around the
default module gain (see electrical parameters)
MinGain
0x00
-20dB gain adjustment (minimum)
DefaultGain
0x28
0dB gain adjustment ('2500 RMS' requirement)
MaxGain
0x50
+20dB gain adjustment (maximum)
43.7.9 PSEL.CLK
Address offset: 0x540
Pin number configuration for PDM CLK signal
Bit number
Id
Reset 0xFFFFFFFF
31 30
B
1 1
29
1
28
1
27
1
26
1
25
1
24
1
23 22 21 20
1 1 1 1
19
1
18
1
17
1
16
1
15
1
14
1
13
1
12
1
11
1
10
1
9
1
8
1
7
1
6
1
5
1
4
A
1
3
A
1
2
A
1
1
A
1
0
A
1
Id RW Field
Value Id
Value
Description
A RW PIN
[0..31]
Pin number
B RW CONNECT
Disconnected
1
Connection
Disconnect
Connected
0
Connect
43.7.10 PSEL.DIN
Address offset: 0x544