Product Specs

43 PDM — Pulse density modulation interface
Page
444
Pin number configuration for PDM DIN signal
Bit number
Id
Reset 0xFFFFFFFF
31 30
B
1 1
29
1
28
1
27
1
26
1
25
1
24
1
23 22 21 20
1 1 1 1
19
1
18
1
17
1
16
1
15
1
14
1
13
1
12
1
11
1
10
1
9
1
8
1
7
1
6
1
5
1
4
A
1
3
A
1
2
A
1
1
A
1
0
A
1
Id RW Field
Value Id
Value
Description
A RW PIN
[0..31]
Pin number
B RW CONNECT
Disconnected
1
Connection
Disconnect
Connected
0
Connect
43.7.11 SAMPLE.PTR
Address offset: 0x560
RAM address pointer to write samples to with EasyDMA
Bit number
31 30
29
28
27
26
25
24
23 22 21 20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Id
A A
A
A
A
A
A
A
A A A A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Reset 0x00000000
0 0
0
0
0
0
0
0
0 0 0 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Id
RW Field
Value Id
Value
Description
A RW SAMPLEPTR Address to write PDM samples to over DMA
43.7.12 SAMPLE.MAXCNT
Address offset: 0x564
Number of samples to allocate memory for in EasyDMA mode
Bit number
Id
Reset 0x00000000
31 30
0 0
29
0
28
0
27
0
26
0
25
0
24
0
23 22 21 20
0 0 0 0
19
0
18
0
17
0
16
0
15
0
14
A
0
13
A
0
12
A
0
11
A
0
10
A
0
9
A
0
8
A
0
7
A
0
6
A
0
5
A
0
4
A
0
3
A
0
2
A
0
1
A
0
0
A
0
Id RW Field
Value Id
Value
Description
A RW BUFFSIZE [0..32767] Length of DMA RAM allocation in number of samples
43.8 Electrical specification
43.8.1 PDM Electrical Specification
Symbol
Description
Min.
Typ.
Max.
Units
I
PDM,stereo
PDM module active current, stereo operation
38
1.4
mA
f
PDM,CLK
PDM clock speed
1.032
MHz
t
PDM,JITTER
Jitter in PDM clock output
20
ns
T
dPDM,CLK
PDM clock duty cycle
40
50
60
%
t
PDM,DATA
Decimation filter delay
5
ms
t
PDM,cv
Allowed clock edge to data valid
125
ns
t
PDM,ci
Allowed (other) clock edge to data invalid
0
ns
t
PDM,s
Data setup time at f
PDM,CLK
=1.024 MHz
65
ns
t
PDM,h
Data hold time at f
PDM,CLK
=1.024 MHz
0
ns
G
PDM,default
Default (reset) absolute gain of the PDM module
3.2
dB
38
Average current including PDM and DMA transfers, excluding clock and power supply base currents