Product Specs

44 I
2
S — Inter-IC sound interface
Page
447
LRCK = MCK / CONFIG.RATIO
TX data is written to the SDOUT pin on the falling edge of SCK, and RX data is read from the SDIN pin on
the rising edge of SCK. The most significant bit (MSB) is always transmitted first.
TX and RX are available in both Master and Slave modes and can be enabled/disabled independently in the
CONFIG.TXEN on page 456 and CONFIG.RXEN on page 456.
Transmission and/or reception is started by triggering the START task. When started and transmission
is enabled (in CONFIG.TXEN on page 456), the TXPTRUPD event will be generated for every
RXTXD.MAXCNT on page 459 number of transmitted data words (containing one or more samples).
Similarly, when started and reception is enabled (in CONFIG.RXEN on page 456), the RXPTRUPD event
will be generated for every RXTXD.MAXCNT on page 459 received data words.
Figure 130: Transmitting and receiving. CONFIG.FORMAT = Aligned, CONFIG.SWIDTH = 8Bit,
CONFIG.CHANNELS = Stereo, RXTXD.MAXCNT = 1.
44.3 Left right clock (LRCK)
The Left Right Clock (LRCK), often referred to as "word clock", "sample clock" or "word select" in I
2
S
context, is the clock defining the frames in the serial bit streams sent and received on SDOUT and SDIN,
respectively.
In I2S mode, each frame contains one left and right sample pair, with the left sample being transferred during
the low half period of LRCK followed by the right sample being transferred during the high period of LRCK.
In Aligned mode, each frame contains one left and right sample pair, with the left sample being transferred
during the high half period of LRCK followed by the right sample being transferred during the low period of
LRCK.
Consequently, the LRCK frequency is equivalent to the audio sample rate.
When operating in Master mode, the LRCK is generated from the MCK, and the frequency of LRCK is then
given as:
LRCK always toggles around the falling edge of the serial clock SCK.
44.4 Serial clock (SCK)
The serial clock (SCK), often referred to as the serial bit clock, pulses once for each data bit being
transferred on the serial data lines SDIN and SDOUT.
LRCK
RXTXD.MAXCNT RXTXD.MAXCNT
Left 0 Right 0 Left 1 RIght 1 Left 2 Right 2 Left 3 Right 3 Left 4
A A A A C C C C E
B
B
B
B
D
D
D
D
F
SCK
SDIN
SDOUT
CPU
TXD.PTR = A
RXD.PTR = B
START
TXPTRUPD
RXPTRUPD
TXD.PTR = C
RXD.PTR = D
TXPTRUPD
TXD.PTR = E
RXPTRUPD
RXD.PTR = F
TXPTRUPD
TXD.PTR = G
RXPTRUPD
RXD.PTR = H