Product Specs

Table Of Contents
44 I
2
S Inter-IC sound interface
Page
457
Transmission (TX) enable.
Bit number
Id
Reset 0x00000001
31 30
0 0
29
0
28
0
27
0
26
0
25
0
24
0
23 22 21 20
0 0 0 0
19
0
18
0
17
0
16
0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
A
1
Id RW Field
Value Id
Value
Description
A RW TXEN Transmission (TX) enable.
Disabled 0 Transmission disabled and now data will be read from theRXD.TXD
address.
Enabled 1 Transmission enabled.
44.10.8 CONFIG.MCKEN
Address offset: 0x510
Master clock generator enable.
Bit number
Id
Reset 0x00000001
31 30
0 0
29
0
28
0
27
0
26
0
25
0
24
0
23 22 21 20
0 0 0 0
19
0
18
0
17
0
16
0
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
A
1
Id RW Field
Value Id
Value
Description
A RW MCKEN
Master clock generator enable.
Disabled
0
Master clock generator disabled and PSEL.MCK not
connected(available as GPIO).
Enabled
1
Master clock generator running and MCK output on PSEL.MCK.
44.10.9 CONFIG.MCKFREQ
Address offset: 0x514
Master clock generator frequency.
Bit number
31 30
29
28
27
26
25
24
23 22 21 20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Id
A A
A
A
A
A
A
A
A A A A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
Reset 0x20000000
0 0
1
0
0
0
0
0
0 0 0 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Id
RW Field
Value Id
Value
Description
A RW MCKFREQ
Master clock generator frequency.
32MDIV2
0x80000000
32 MHz / 2 = 16.0 MHz
32MDIV3
0x50000000
32 MHz / 3 = 10.6666667 MHz
32MDIV4
0x40000000
32 MHz / 4 = 8.0 MHz
32MDIV5
0x30000000
32 MHz / 5 = 6.4 MHz
32MDIV6
0x28000000
32 MHz / 6 = 5.3333333 MHz
32MDIV8
0x20000000
32 MHz / 8 = 4.0 MHz
32MDIV10
0x18000000
32 MHz / 10 = 3.2 MHz
32MDIV11
0x16000000
32 MHz / 11 = 2.9090909 MHz
32MDIV15
0x11000000
32 MHz / 15 = 2.1333333 MHz
32MDIV16
0x10000000
32 MHz / 16 = 2.0 MHz
32MDIV21
0x0C000000
32 MHz / 21 = 1.5238095
32MDIV23
0x0B000000
32 MHz / 23 = 1.3913043 MHz
32MDIV30
0x08800000
32 MHz / 30 = 1.0666667 MHz
32MDIV31
0x08400000
32 MHz / 31 = 1.0322581 MHz
32MDIV32
0x08000000
32 MHz / 32 = 1.0 MHz
32MDIV42
0x06000000
32 MHz / 42 = 0.7619048 MHz
32MDIV63
0x04100000
32 MHz / 63 = 0.5079365 MHz
32MDIV125
0x020C0000
32 MHz / 125 = 0.256 MHz
44.10.10 CONFIG.RATIO
Address offset: 0x518
MCK / LRCK ratio.