Product Specs

47 PWM — Pulse width modulation
Page
496
PWM
START
STOP
SEQSTART[0]
SEQSTART[1]
STARTED
STOPPED
SEQSTARTED[0]
SEQSTARTED[1]
NEXTSTEP
SEQEND[0]
SEQEND[1]
PSEL.OUT[0]
PSEL.OUT[1]
PSEL.OUT[2]
PSEL.OUT[3]
Carry/Reload
PWM_CLK
PRESCALER
COUNTERTOP
Wave Counter
COMP3
COMP2
COMP1
COMP0
SEQ[n].REFRESH
Decoder
47 PWM — Pulse width modulation
The PWM module enables the generation of pulse width modulated signals on GPIO. The module
implements an up or up-and-down counter with four PWM channels that drive assigned GPIOs.
Three PWM modules can provide up to 12 PWM channels with individual frequency control in groups of up to
four channels. Furthermore, a built-in decoder and EasyDMA capabilities make it possible to manipulate the
PWM duty cycles without CPU intervention. Arbitrary duty-cycle sequences are read from Data RAM and can
be chained to implement ping-pong buffering or repeated into complex loops.
Listed here are the main features of one PWM module:
• Fixed PWM base frequency with programmable clock divider
• Up to four PWM channels with individual polarity and duty-cycle values
• Edge or center-aligned pulses across PWM channels
• Multiple duty-cycle arrays (sequences) defined in Data RAM
• Autonomous and glitch-free update of duty cycle values directly from memory through EasyDMA
• Change of polarity, duty-cycle, and base frequency possibly on every PWM period
• Data RAM sequences can be repeated or connected into loops
DATA RAM
Sequence 0
Sequence 1
Figure 141: PWM Module
47.1 Wave counter
The wave counter is responsible for generating the pulses at a duty-cycle that depends on the compare
values, and at a frequency that depends on COUNTERTOP.
There is one common 15-bit counter with four compare channels. Thus, all four channels will share the same
period (PWM frequency), but can have individual duty-cycle and polarity. The polarity is set by the value
read from RAM (see Figure 144: Decoder memory access modes on page 499), while the MODE register
controls if the counter counts up, or up and down. The timer top value is controlled by the COUNTERTOP
register. This register value in conjunction with the selected PRESCALER of the PWM_CLK will result in a
given PWM period. A COUNTERTOP value smaller than the compare setting will result in a state where no
PWM edges are generated. Respectively, OUT[n] is held high, given that the polarity is set to FallingEdge.
All the compare registers are internal and can only be configured through the decoder presented later.
COUNTERTOP can be safely written at any time. It will get sampled following a START task. If
DECODER.LOAD is anything else than WaveForm, it will also get sampled following a STARTSEQ[n] task,
EasyDMA