Product Specs

47 PWM — Pulse width modulation
Page
499
47.2 Decoder with EasyDMA
The decoder uses EasyDMA to take PWM parameters stored in Data RAM by ways of EasyDMA and
updates the internal compare registers of the wave counter based on the mode of operation.
The mentioned PWM parameters are organized into a sequence containing at least one half word (16 bit).
Its most significant bit[15] denotes the polarity of the OUT[n] while bit[14:0] is the 15-bit compare value. See
below for further details of these RAM defined registers.
Bit number
Id
Reset 0x00000000
31 30
0 0
29
0
28
0
27
0
26
0
25
0
24
0
23 22 21 20
0 0 0 0
19
0
18
0
17
0
16
0
15
B
0
14
A
0
13
A
0
12
A
0
11
A
0
10
A
0
9
A
0
8
A
0
7
A
0
6
A
0
5
A
0
4
A
0
3
A
0
2
A
0
1
A
0
0
A
0
Id RW Field
Value Id
Value
Description
A RW COMPARE
Duty cycle setting - value loaded to internal compare register
B RW POLARITY
RisingEdge
0
Edge polarity of GPIO.
First edge within the PWM period is rising
FallingEdge
1
First edge within the PWM period is falling
The DECODER register controls how the RAM content is interpreted and loaded to the internal compare
registers. The LOAD field can be used to control if the RAM values are loaded to all compare channels - or
alternatively to update a group or all channels with individual values. Figure 144: Decoder memory access
modes on page 499 illustrates how the parameters stored in RAM are organized and routed to the various
compare channels in the different modes.
A special mode of operation is available when DECODER.LOAD is set to WaveForm. In this mode, up to
three PWM channels can be enabled - OUT[0] to OUT[2]. In RAM, four values are loaded at a time: the
first, second and third location are used to load the values, and the fourth RAM location is used to load the
COUNTERTOP register. This way one can have up to three PWM channels with a frequency base that
changes on a per PWM period basis. This mode of operation is useful for arbitrary wave form generation in
applications such as LED lighting.
The register SEQ[n].REFRESH=N (one per sequence n=0 or 1) will instruct a new RAM stored pulse width
value on every (N+1)
th
PWM period. Setting the register to zero will result in a new duty cycle update every
PWM period as long as the minimum PWM period is observed.
Note that registers SEQ[n].REFRESH and SEQ[n].ENDDELAY are ignored when
DECODER.MODE=NextStep . The next value is loaded upon receiving every NEXTSTEP task.
DECODER.LOAD=Common
P
COMP0
DECODER.LOAD=Grouped
DECODER.LOAD=Single
SEQ[n].PTR
O
L
P
O
L
Increasing Data
RAM Address
P
O
L
COMPARE
COMPARE
...
COMPARE
COMP1
COMP2
COMP3
COMP0
COMP1
COMP2
COMP3
COMP0
COMP1
COMP2
COMP3
COMP0
COMP1
COMP2
COMP3
COMP0
COMP1
DECODER.LOAD=WaveForm
COMP0
COMP1
COMP2
COUNTERTOP
Figure 144: Decoder memory access modes
P
O
L
P
O
L
...
P
O
L
COMPARE
COMPARE
COMPARE
P
O
COMPARE
COMP0
L
P
O
COMPARE
COMP1
L
P
O
COMPARE
COMP2
L
P
O
COMPARE
COMP3
L
P
O
L
P
O
L
P
O
L
TOP
COMPARE
COMPARE
COMPARE